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high performance 10-bit display interface ad9984a rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 10-bit, analog-to-digital converters 170 msps maximum conversion rate low pll clock jitter at 170 msps automatic gain matching automated offset adjustment 2:1 input mux power-down via dedicated pin or serial register 4:4:4, 4:2:2, and ddr output format modes variable output drive strength odd/even field detection external clock input regenerated hsync output programmable output high impedance control hsyncs per vsync counter sync-on-green (sog) pulse filter pb-free package applications advanced tvs plasma display panels lcdtv hdtv rgb graphics processing lcd monitors and projectors scan converters functional block diagram sync processing pll power management sogout odd/even field hsout vsout/a0 voltage refs serial register sda scl filt clamp extck/coast hsync0 hsync1 ad9984a y/green out cb/cr/red out refhi reflo datack 2:1 mux pr/red in0 pr/red in1 y/green in0 y/green in1 vsync1 vsync0 2:1 mux sogin0 sogin1 2:1 mux output data formatter cb/blue out clamp 10 10 auto offset auto gain 10-bit adc pga pb/blue in0 pb/blue in1 2:1 mux clamp 10 10 auto offset auto gain 10-bit adc pga 2:1 mux clamp 10 10 auto offset auto gain 10-bit adc pga 2:1 mux 06476-001 figure 1. general description the ad9984a is a complete 10-bit, 170 msps, monolithic analog interface optimized for capturing ypbpr video and rgb graphics signals. its 170 msps encode rate capability and full power analog bandwidth of 300 mhz support all hdtv video modes up to 1080p, as well as graphics resolutions up to uxga (1600 1200 at 60 hz). the ad9984a includes a 170 mhz triple adc with an internal reference, a pll, and programmable gain, offset, and clamp control. the user provides only a 1.8 v power supply and an analog input. three-state cmos outputs can be powered from 1.8 v to 3.3 v. the ad9984a on-chip pll generates a sample clock from the tri-level sync (for ypbpr video) or the horizontal sync (for rgb graphics). sample clock output frequencies range from 10 mhz to 170 mhz. with internal coast generation, the pll maintains its output frequency in the absence of a sync input. a 32-step sampling clock phase adjustment is provided. output data, sync, and clock phase relationships are maintained. the auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. the auto channel-to-channel gain- matching feature can be enabled to minimize any gain mismatches between the three channels. the ad9984a also offers full sync processing for composite sync and sync-on-green applications. a clamp signal is generated internally or can be provided by the user through the clamp input pin. fabricated in an advanced cmos process, the ad9984a is provided in a space-saving, pb-free, 80-lead low profile quad flat package (lqfp) or 64-lead lead frame chip scale package (lfcsp) and is specified over the 0c to 70c temperature range.
ad9984a rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 analog interface characteristics ................................................ 3 absolute maximum ratings ............................................................ 5 explanation of test levels ........................................................... 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 theory of operation ...................................................................... 11 digital inputs .............................................................................. 11 analog input signal handling .................................................. 11 hsync and vsync inputs ............................................................ 11 serial control port ..................................................................... 11 output signal handling ............................................................. 11 clamping ..................................................................................... 11 gain and offset control ............................................................ 12 sync-on-green ............................................................................ 13 reference bypassing ................................................................... 13 clock generation ....................................................................... 14 sync processing ........................................................................... 16 power management .................................................................... 19 timing diagrams ........................................................................ 19 hsync timing ............................................................................. 20 coast timing ............................................................................... 21 output formatter ....................................................................... 21 2-wire serial control port ............................................................ 22 data transfer via serial interface ............................................. 22 2-wire serial register map ........................................................... 24 2-wire serial control registers .................................................... 30 chip identification ..................................................................... 30 pll divider control .................................................................. 30 clock generator control .......................................................... 30 phase adjust ................................................................................ 30 input gain ................................................................................... 30 input offset ................................................................................. 31 hsync control ............................................................................. 31 vsync control ............................................................................. 32 coast and clamp controls ........................................................ 33 sog control ............................................................................... 34 input and power control ........................................................... 35 output control ........................................................................... 35 sync processing .......................................................................... 36 detection status .......................................................................... 37 polarity status ............................................................................. 37 hsync count ............................................................................... 38 test registers ............................................................................... 38 pcb layout recommendations .................................................... 40 analog interface inputs ............................................................. 40 outputs (both data and clocks) .............................................. 40 digital inputs .............................................................................. 41 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 revision history 7 /07revision 0: initial version
ad9984a rev. 0 | page 3 of 44 specifications analog interface characteristics v d = 1.8 v, v dd = 3.3 v, pv d = 1.8 v, dav dd = 1.8 v, adc clock = maximum conversion rate, full temperature range = 0c to 70c. table 1. electrical characteristics ad9984akstz-140 ad9984akcpz-140 ad9984akstz-170 ad9984akcpz-170 parameter temp test level 1 min typ max min typ max unit resolution number of bits 10 10 bits lsb size 0.098 0.098 % of full scale (fs) dc accuracy differential nonlinearity 25c i 0.6 +1.8/?1.0 0.7 +1.9/?1.0 lsb full vi +1.9/?1.0 +2.0/?1.0 lsb integral nonlinearity 25c i 2.35 7.0 2.35 8.5 lsb full vi 9.0 9.0 lsb no missing codes full vi gnt 2 gnt 2 analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25c v 125 125 ppm/c input bias current 25c iv 1 1 a full iv 1 1 a input full-scale matching full vi 1 1 % fs offset adjustment range full vi 50 50 % fs switching performance maximum conversion rate full vi 140 170 msps minimum conversion rate full iv 10 10 msps clock to data skew (t skew ) full iv ?0.5 +2.0 ?0.5 +2.0 ns t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 0 0 s t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s maximum pll clock rate full vi 140 170 mhz minimum pll clock rate full iv 10 10 mhz sampling phase tempco full iv 15 15 ps/c digital inputs input voltage, high (v ih ) full vi 1.0 1.0 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (i ih ) full v ?1.0 ?1.0 a input current, low (i il ) full v 1.0 1.0 a input capacitance 25c v 2 2 pf digital outputs output voltage, high (v oh ) full vi v dd ? 0.1 v dd ? 0.1 v output voltage, low (v ol ) full vi 0.1 0.1 v duty cycle (datack) full iv 45 50 55 45 50 55 % output coding binary binary
ad9984a rev. 0 | page 4 of 44 ad9984akstz-140 ad9984akcpz-140 ad9984akstz-170 ad9984akcpz-170 parameter temp test level 1 min typ max min typ max unit power supply v d supply voltage full iv 1.7 1.8 1.9 1.755 1.8 1.9 v v dd supply voltage full iv 1.7 3.3 3.47 1.7 3.3 3.47 v pv d supply voltage full iv 1.7 1.8 1.9 1.7 1.8 1.9 v dav dd supply voltage full iv 1.7 1.8 1.9 1.7 1.8 1.9 v v d supply current (i d ) 25 c v 250 255 ma v dd supply current (i dd ) 25 c v 31 34 ma pv d supply current (ipv d ) 25 c v 9 9 ma dav dd supply current (ida vdd ) 25 c v 16 19 ma total power dissipation full vi 710 740 mw power-down supply current full vi 10 10 ma power-down dissipation full vi 18 18 mw dynamic performance analog bandwidth, full power 25c v 300 300 mhz crosstalk full v 60 60 dbc 1 see the explanation of test levels section. 2 guaranteed by design, not production tested.
ad9984a rev. 0 | page 5 of 44 absolute maximum ratings table 2. parameter rating v d 1.98 v v dd 3.6 v pv d 1.98 v dav dd 1.98 v analog inputs v d to 0.0 v refhi v d to 0.0 v reflo v d to 0.0 v digital inputs 5 v to 0.0 v digital output current 20 ma operating temperature range ?25c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and characterization testing. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 80-lead lqfp 35 16 c/w 64-lead lfcsp 35 16 c/w esd caution
ad9984a rev. 0 | page 6 of 44 pin configurations and function descriptions 2 b ain0 3 gnd 4 b ain1 7 gnd 6 g ain0 5 v d (1.8v) 1 v d (1.8v) 8 sogin0 9 v d (1.8v) 10 g ain1 12 sogin1 13 v d (1.8v) 14 r ain0 15 gnd 16 r ain1 17 pwrdn 18 reflo 19 nc 20 refhi 11 gnd 59 58 57 54 55 56 60 53 52 blue 4 blue 5 blue 6 blue 9 blue 8 blue 7 blue 3 gnd v dd (3.3v) 51 green 0 49 green 2 48 green 3 47 green 4 46 green 5 45 green 6 44 green 7 43 green 8 42 green 9 41 dav dd (1.8v) 50 green 1 21 o/e field 22 vsout/a0 23 hsout 24 sogout 25 datack 26 v dd (3.3v) 27 gnd 28 red 9 29 red 8 30 red 7 31 red 6 32 red 5 33 red 4 34 red 3 35 red 2 36 red 1 37 red 0 38 v dd (3.3v) 39 gnd 40 gnd 80 gnd 79 pv d (1.8v) 78 filt 77 gnd 76 pv d (1.8v) 75 gnd 74 pv d (1.8v) 73 clamp 72 extck/coast 71 vsync0 70 hsync0 69 vsync1 68 hsync1 67 scl 66 sda 65 gnd 64 v dd (3.3v) 63 blue 0 62 blue 1 61 blue 2 ad9984a top view (not to scale) 06476-002 nc = no connect pin 1 indicator figure 2. 80-lead l qfp pin configuration
ad9984a rev. 0 | page 7 of 44 0 6476-020 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 green 7 green 8 green 9 green 6 green 5 green 4 green 3 green 2 green 1 green 0 blue 9 blue 8 blue 4 blue 5 blue 6 blue 7 blue 3 blue 2 blue 1 blue 0 v dd sda scl hsync1 vsync1 hsync0 vsync0 extck/coast pv d filt pv d clamp o/e field refhi reflo pwrdn r ain1 r ain0 v d sogin1 g ain1 v d sogin0 g ain0 v d b ain0 b ain1 v d dav dd red 2 red 1 red 0 red 3 red 4 red 5 red 6 red 7 red 8 red 9 v dd vsout/a0 hsout sogout datack ad9984a top view (not to scale) 29 pin 1 indicator figure 3. 64-lead lfcsp pin configuration table 4. complete pin configuration list pin number pin type 80-lead lqfp 64-lead lfcsp mnemonic function value inputs 14 43 r ain0 channel 0 analog input for converter r 0.0 v to 1.0 v 16 44 r ain1 channel 1 analog input for converter r 0.0 v to 1.0 v 6 37 g ain0 channel 0 analog input for converter g 0.0 v to 1.0 v 10 40 g ain1 channel 1 analog input for converter g 0.0 v to 1.0 v 2 34 b b ain0 channel 0 analog input for converter b 0.0 v to 1.0 v 4 35 b b ain1 channel 1 analog input for converter b 0.0 v to 1.0 v 70 26 hsync0 horizontal sync input for channel 0 3.3 v cmos 68 24 hsync1 horizontal sync input for channel 1 3.3 v cmos 71 27 vsync0 vertical sync input for channel 0 3.3 v cmos 69 25 vsync1 vertical sync input for channel 1 3.3 v cmos 8 38 sogin0 input for sync-on-green channel 0 0.0 v to 1.0 v 12 41 sogin1 input for sync-on-green channel 1 0.0 v to 1.0 v 72 28 extck 1 external clock input 3.3 v cmos 73 29 clamp external clamp input signal 3.3 v cmos 72 28 coast 1 external pll coast signal input 3.3 v cmos 17 45 pwrdn power-down control 3.3 v cmos
ad9984a rev. 0 | page 8 of 44 pin number pin type 80-lead lqfp 64-lead lfcsp mnemonic function value outputs 28 to 37 54 to 63 red[9:0] outputs of converter r; bit 9 is the msb 3.3 v cmos 42 to 51 1 to 10 green[9:0] outputs of converter g; bit 9 is the msb 3.3 v cmos 54 to 63 11 to 20 blue[9:0] outputs of converter b; bit 9 is the msb 3.3 v cmos 25 52 datack data output clock 3.3 v cmos 23 50 hsout hsync output clock (phase -aligned with datack) 3.3 v cmos 22 49 vsout 2 vsync output clock 3.3 v cmos 24 51 sogout sync-on-green slicer output 3.3 v cmos 21 48 o/e field odd/even field output 3.3 v cmos references 78 31 filt connection for external filter components for internal pll 18 46 reflo connection for external capacitor for input amplifier 20 47 refhi connection for external capacitor for input amplifier power supply 1, 5, 9, 13 33, 36, 39, 42 v d analog power supply 1.8 v 26, 38, 52, 64 21, 53 v dd output power supply 1.8 v to 3.3 v 74, 76, 79 30, 32 pv d pll power supply 1.8 v 41 64 dav dd digital logic power supply 1.8 v 3, 7, 11, 15, 27, 39, 40, 53, 65, 75, 77, 80 n/a gnd ground 0 v control 66 22 sda serial port data i/o 3.3 v cmos 67 23 scl serial port data clock (100 khz maximum) 3.3 v cmos 22 49 a0 2 serial port address input 3.3 v cmos 1 extck and coast share the same pin. 2 vsout and a0 share the same pin.
ad9984a rev. 0 | page 9 of 44 table 5. pin function descriptions mnemonic function description r ain0 analog input for the red channel 0 g ain0 analog input for the green channel 0 b b ain0 analog input for the blue channel 0 r ain1 analog input for the red channel 1 g ain1 analog input for the green channel 1 b b ain1 analog input for the blue channel 1 these high impedance inputs accept the red, green, and blue channel graphics signals, respectively. the three channels are identical and can be used for any colors, but colors are assigned for convenient reference. they accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. refer to figure 4 and figure 5 . hsync0 horizontal sync input channel 0 hsync1 horizontal sync input channel 1 these inputs receive a logic signal that es tablishes the horizontal timing reference and provides the frequency reference for pixel clock generation. the logic sense of these pins can be automatically determined by the chip or manually controlled by serial register 0x12, bits[5:4] (hsync polarity). only the leading edge of hsync is used by the pll; the trailing edge is used in clamp timing. when hsync pola rity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. these inputs in clude a schmitt trigger for noise immunity. vsync0 vertical sync input channel 0 vsync1 vertical sync input channel 1 these inputs for vertical sync provide timin g information for generation of the field (odd/even) and internal coast generation . the logic sense of this pin can be automatically determined by the chip or manu ally controlled by serial register 0x14, bits[5:4] (vsync polarity). sogin0 sync-on-green input channel 0 sogin1 sync-on-green input channel 1 these inputs help process signals with embedded sync, typically on the green channel. these pins connect to a high speed comparator with an internally generated threshold. the threshold level can be programmed in 8 mv steps to any voltage between 8 mv and 256 mv above the negative peak of the inp ut signal. the default voltage threshold is 128 mv. when connected to an ac-coupled graphics signal with embedded sync, a noninverting digital output is produced on sogout. this output is usually a composite sync signal, containing both vertical and ho rizontal sync information that must be separated before passing the horizontal sync signal for hsync processing. when not used, these inputs should be left unconnected . for more details abo ut this function and how it should be configured, refer to the sync-on-green section. clamp external clamp input (optional) this logic input can be used to define the t ime during which the input signal is clamped to ground or midscale. it should be exercised when the reference dc level is known to be present on the analog input channels, typica lly during the back porch of the graphics signal. the clamp pin is enabled by setting the co ntrol bit clamp function to 1, (register 0x18, bit 4; default is 0). when disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the hsync input. the logic sense of this pin can be automatically determined by the chip or controlled by clamp polarity (register 0x1b, bits[7:6]). when not used, this pin can be left unconnected (there is an internal pull-down resistor) and the clamp function programmed to 0. extck/coast external clock (extck) this pin has dual functionality. extck allows the insertion of an external clock source rather than the internally generated, pll locked clock. extck is enabled by progra mming register 0x03, bit 2 to 1. this extck function does not affect the coast function. optional coast input to clock generator (coast) coast can be used to cause the pixel clock generator to stop synchronizing with hsync and continue to produce a clock at its curren t frequency and phase. this is useful when processing signals from sources that fail to produce hsync pulses during the vertical interval. the coast signal is generally not required for pc-generated signals. the logic sense of this pin can be determined automatically or controlled by coast polarity (register 0x18, bits[7:6]). when this function and the extck function are not used, this pin can be grounded and coast polarity prog rammed to 1. input coast polarity defaults to 1 at power-up. this coast function does not affect the extck function. pwrdn power-down control (pwrdn) pwrdn allows for manual power-down control. if manual power-down control is selected (register 0x1e, bit 4),and this pin is not used , it is recommended to set the pin polarity (register 0x1e, bit 2) to active high and hardwire this pin to ground with a 10 k resistor. reflo, refhi input amplifier reference reflo and refhi are connected together through a 10 f capacitor. these are used for stability in the input adc circuitry. see figure 6 .
ad9984a rev. 0 | page 10 of 44 mnemonic function description filt external filter connection for proper operation, the pixel clock generator pll requires an external filter. connect the filter shown in figure 8 to this pin. for optimal performance, minimize noise and parasitics on this node. for more information, see the pcb layout recommendations section. hsout horizontal sync output this pin is a reconstructed and phase-alig ned version of the hsync input. both the polarity and duration of this output can be programmed via serial bus registers. by maintaining alignment with datack and the main data outputs (red[9:0], green[9:0], blue[9:0]), data timing with respect to hsync can always be determined. vsout/a0 vertical sync output (vsout) this pin has dual functionality. vsout can either be a separated vsync from a composite signal or a direct pass through of the vsync signal. the polarity of this output can be controlled via a serial bus bit. the placement and duration in all modes can be set by the graphics transmitter or the duration can be set by register 0x14, bit 1 and register 0x15, bits[7:0]. this vsout function does not affect the a0 function. serial port address input 0 (a0) a0 selects the lsb of the serial port device address, allowing two parts from analog devices, inc., to be on the same serial bus. a high impedance (10 k), external pull-up resistor enables this pin to be read at power- up as 1. this a0 function does not interfere with the vsout function. for more deta ils on a0, see the description in the 2-wire serial control port section. sogout sync-on-green slicer output this pin outputs one of four possible signals (controlled by register 0x1d, bits[1:0]): raw soginx, raw hsyncx, regenerated hsync from the filter, or the filtered hsync. see figure 9 to view how this pin is connected. other than slicing off sog, the output from this pin receives no additional processing on the ad9984a. vsync separation is performed via the sync separator. o/e field odd/even field bit for interlaced video this output identifies whether the current fiel d (in an interlaced signal) is odd or even. sda serial port data i/o data i/o for the i 2 c? serial port. scl serial port data clock clock for the i 2 c serial port. red[9:0] data output, red channel green[9:0] data output, green channel blue[9:0] data output, blue channel the main data outputs. bit 9 is the msb. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack and hs out outputs are also moved to maintain the timing relationship among the signals. datack data clock output this is the main clock output signal used to strobe the output data and hsout into external logic. four possible output clocks can be selected with register 0x20, bits[7:6]. three of these are related to the pixel clock (pixel clock, 90 phase-shifted pixel clock, and 2 frequency pixel clock). they are prod uced by the internal pll clock generator or by extck, and are synchronous with the pixel sampling clock. the fourth option for the data clock output is an internally generated 0.5 pixel clock. the sampling time of the internal pixel clock can be changed by adjusting the phase register (register 0x04). when this is changed, the pixel-related datack timing is also shifted. the data (red[9:0], green[9:0], blue[9:0]), datack, and hsout outputs are moved to maintain the timing relationship among the signals. v d (1.8 v) main power supply these pins supply power to the main elements of the circuit. they should be as quiet and as filtered as possible. v dd (1.8 v to 3.3 v) digital output power supply a large number of output pins (up to 35) switc hing at high speed (up to 170 mhz) generates large amounts of power supply transients (noise). these supply pins are identified separately from the v d pins. as a result, special care must be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad 9984a is interfacing with lower voltage logic, v dd can be connected to a lower supply voltage (as low as 1.8 v) for compatibility. pv d (1.8 v) clock generator power supply the most sensitive portion of the ad9984a is the clock generation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide quiet, noise-free power to these pins. dav dd (1.8 v) digital input power supply this supplies power to the digital logic. it is recommended to connect this pin to the v d supply. gnd ground the ground return for all on-chip circuitry. it is recommended that the ad9984a be assembled on a single solid ground plane with careful attention to ground current paths.
ad9984a rev. 0 | page 11 of 44 theory of operation the ad9984a is a fully integrated solution for capturing and digitizing analog rgb or ypbpr signals for display on advanced tvs, flat panel monitors, projectors, and other types of digital displays. implemented in a high performance cmos process, the interface can capture signals with pixel rates up to 170 mhz. the ad9984a includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. all controls are programmable via a 2-wire serial interface (i 2 c). full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. with a typical power dissipation of less than 900 mw and an operating temperature range of 0c to 70c, the device requires no special environmental considerations. digital inputs all digital inputs on the ad9984a operate to 3.3 v cmos levels. the following digital inputs are 5 v tolerant (that is, applying 5 v to them does not cause any damage): hsync0, hsync1, vsync0, vsync1, sogin0, sogin1, sda, scl, and clamp. analog input signal handling the ad9984a has six, high impedance, analog input pins for the red, green, and blue channels. they accommodate signals ranging from 0.5 v to 1.0 v p-p. signals are typically brought onto the interface board with a dvi-i connector, a 15-pin d connector, or rca connectors. the ad9984a should be located as close as possible to the input connector. signals should be routed using matched- impedance traces (normally 75 ) to the ic input pins. at the input pins, the signal should be resistively terminated (75 to the signal ground return) and capacitively coupled to the ad9984a inputs through 47 nf capacitors. these capacitors form part of the dc restoration circuit. in an ideal world of perfectly matched impedances, the best performance can be obtained with the widest possible signal bandwidth. the wide bandwidth inputs of the ad9984a (300 mhz) can track the input signal continuously as it moves from one pixel level to the next and can digitize the pixel during a long, flat pixel time. in many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. this makes it more difficult to establish a sampling phase that provides good image quality. a small inductor in series with the input is shown to be effective in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. using a high speed, signal chip, bead inductor (such as the fair-rite 2508051217z0) in the circuit shown in figure 4 provides good results in most applications. rgb input r ain g ain b ain 75? 06476-003 47n f figure 4. analog input interface circuit hsync and vsync inputs the interface also accepts hsync and vsync signals, which are used to generate the pixel clock, clamp timing, and coast and field information. these can be either a sync signal directly from the graphics source, or a preprocessed ttl- or cmos- level signal. the hsync input includes a schmitt trigger buffer for immunity to noise and signals with long rise times. in typical pc-based graphic systems, the sync signals are simply ttl-level drivers feeding unshielded wires into the monitor cable. as such, no termination is required. serial control port the serial control port is designed for 3.3 v logic; however, it is tolerant of 5 v logic signals. refer to the 2-wire serial control port section for more information. output signal handling the digital outputs operate from 1.8 v to 3.3 v (v dd ). clamping rgb clamping to properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board adcs. most graphics systems produce rgb signals with black at ground and white at approximately 0.75 v. however, if sync signals are embedded in the graphics, the sync tip is often at ground, black is at 300 mv, and white is at approximately 1.0 v. some common rgb line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. this introduces a 700 mv dc offset to the signal, which must be removed for proper capture by the ad9984a. the key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. an offset is then introduced that results in the adc producing a black output (code 0x00) when the known black input is present. the offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. in most pc graphics systems, black is transmitted between active video lines. with crt displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image.
ad9984a rev. 0 | page 12 of 44 in systems with embedded sync, a blacker-than-black signal (hsync) is briefly produced to signal the crt that it is time to begin a retrace. because the input is not at black level at this time, it is important to avoid clamping during hsync. fortunately, there is usually a period following hsync (called the back porch) where a good black reference is provided. this is the time when clamping should be done. the clamp timing can be established by simply exercising the clamp pin at the appropriate time with clamp source (register 0x18, bit 4) = 1. the polarity of this signal is set by the clamp polarity bits (register 0x1b, bits[7:6]). a simpler method of clamp timing employs the ad9984a internal clamp timing generator. the clamp placement register (register 0x19) is programmed with the number of pixel periods that should pass after the trailing edge of hsync before clamping starts. a second register, clamp duration (register 0x1a), sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. although hsync duration can widely vary, the clamp timing is referenced to the trailing edge of hsync because the back porch (black reference) always follows hsync. an effective starting point for establishing clamping is to set the clamp placement to 0x04 (providing 4 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 0x28 (giving the clamp 40 pixel periods to reestablish the black reference). clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. the value of this capacitor affects the performance of the clamp. if it is too small, there is a significant amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, it takes a long time for the clamp to recover from a large change in incoming signal offset. the recommended value (100 nf) results in recovering from a step error of 100 mv to within 1 lsb in 60 lines with a clamp duration of 20 pixel periods on a 85 hz xga signal. ypbpr clamping ypbpr graphic signals are slightly different from rgb signals in that the dc reference level (black level in rgb signals) of color difference signals is at the midpoint of the video signal rather than at the bottom. the three inputs are composed of luminance (y) and color difference (pb and pr) signals. for color difference signals, it is necessary to clamp to the midscale range of the adc range (512) rather than to the bottom of the adc range (0), while the y channel is clamped to ground. clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. each of the three converters has its own selection bit to enable them to be independently clamped to midscale or ground. these bits are located in register 0x18, bits[3:1]. the midscale reference voltage is internally generated for each converter. gain and offset control the ad9984a contains three programmable gain amplifiers (pgas), one for each of the three analog inputs. the range of the pga is sufficient to accommodate input signals with inputs ranging from 0.5 v to 1.0 v full scale. the gain is set in three 9-bit registers, red gain (register 0x05, register 0x06), green gain (register 0x07, register 0x08), and blue gain (register 0x09, register 0x0a). for each register, a gain setting of 0d corresponds to the highest gain, while a gain setting of 511d corresponds to the lowest gain. note that increasing the gain setting results in an image with less contrast. the offset control shifts the analog input, resulting in a change in brightness. three 11-bit registers, red offset (register 0x0b, register 0x0c), green offset (register 0x0d, register 0x0e), and blue offset (register 0x0f, register 0x10) provide inde- pendent settings for each channel. note that the function of the offset register depends on whether auto-offset is enabled (register 0x1b, bit 5). if manual offset is used, nine bits of the offset registers (for the red channel, register 0x0b, bits[6:0] plus register 0x0c, bits[7:6]) control the absolute offset added to the channel. the offset control provides 255 lsbs of adjustment range, with 1 lsb of offset corresponding to 1 lsb of output code. automatic offset in addition to the manual offset adjustment mode, the ad9984a also includes circuitry to automatically calibrate the offset for each channel. by monitoring the output of each adc during the back porch of the input signals, the ad9984a can self-adjust to eliminate any offset errors in its own adc channels and any offset errors present on the incoming graphics or video signals. to activate the auto-offset mode, set register 0x1b, bit 5 to 1. next, the target code registers (register 0x0b through register 0x10) must be programmed. the values programmed into the target code registers should be the output code desired from the ad9984a during the back porch reference time. for example, for rgb signals, all three registers are normally programmed to code 2, while for ypbpr signals, the green (y) channel is normally programmed to code 2, and the blue and red channels (pb and pr) are normally set to 512. the target code registers have 11 bits per channel and are in twos complement format. this allows any value between ?1024 and +1023 to be programmed. although any value in this range can be programmed, the ad9984a offset range may not be able to reach every value. intended target code values range from (but are not limited to) ?160 to ?1 and +1 to +160 when ground clamping, and 350 to 670 when midscale clamping. note that a target code of 0 is not valid.
ad9984a rev. 0 | page 13 of 44 negative target codes are included to duplicate a feature that is present with manual offset adjustment. the benefit that is mimicked is the ability to easily adjust brightness on a display. by setting the target code to a value that does not correspond to the ideal adc range, the end result is an image that is brighter or darker. a target code higher than ideal results in a brighter image, whereas a target code lower than ideal results in a darker image. the ability to program a target code offers a large degree of freedom and flexibility. although all channels are set to either 1 or 512 in most cases, the flexibility to select other values makes it possible to insert intentional skews between channels. it also allows the adc range to be skewed so that voltages outside of the normal range can be digitized. for example, setting the target code to 40 allows the sync tip, which is normally below black level, to be digitized and evaluated. the internal logic for the auto-offset circuit requires 16 data clock cycles to perform its function. this operation is executed immediately after the clamping pulse. therefore, it is important to end the clamping pulse signal at least 16 data clock cycles before active video. this is true whether using the ad9984a internal clamp circuit or an external clamp signal. the auto- offset function can be programmed to run continuously or on a one-time basis (see the 0x2cbit[4] auto-offset hold section). in continuous mode, the update frequency can be programmed (register 0x1b, bits[4:3]). continuous operation with updates every 192 hsyncs is recommended. guidelines for basic auto-offset operation are shown in tabl e 6 and table 7 . table 6. rgb auto-offset register settings register value comments 0x0b 0x00 sets red target to 4. 0x0c 0x80 must be written. 0x0d 0x00 sets green target to 4. 0x0e 0x80 must be written. 0x0f 0x00 sets blue target to 4. 0x10 0x80 must be written. 0x18, bits[3:1] 000 sets red, green, and blue channels to ground clamp. 0x1b, bits[5:3] 110 selects update rate to every 192 clamps and enables auto-offset. table 7. ypbpr auto-offset register settings register value comments 0x0b 0x40 sets pr (red) target to 512. 0x0c 0x00 must be written. 0x0d 0x00 sets y (green) target to 4. 0x0e 0x80 must be written. 0x0f 0x40 sets pb (blue) target to 512. 0x10 0x00 must be written. 0x18, bits[3:1] 101 sets pb, pr to midscale clamp and y to ground clamp. 0x1b, bits[5:3] 110 selects update rate to every 192 clamps and enables auto-offset. automatic gain matching the ad9984a includes circuitry to match the gains between the three channels to within 1% of each other. matching the gains of each channel is necessar y to achieve good color balance on a display. on products without this feature, gain matching is achieved by writing software that evaluates the output of each channel, calculates gain mismatches, and then writes values to the gain registers of each channel to compensate. with the auto gain matching function, this software routine is no longer needed. to activate auto gain matching, set register 0x3c, bits[2:0] to 110. auto gain matching has similar timing requirements to auto offset. it requires 16 data clock cycles to perform its function, starting immediately after the end of the clamp pulse. unlike auto offset, auto gain matching does not require that these 16 clock cycles occur during the back porch reference time, although it is recommended. during auto gain matching operation, the data outputs of the ad9984a are frozen (held at the value they had just prior to operation). the auto gain matching function can be programmed to run continuously or on a one-time basis (see the 0x3cbit[3] auto gain matching hold section). in continuous mode, the update frequency can be programmed (register 0x1b, bits[4:3]). continuous operation with updates every 192 hsyncs is recommended. sync-on-green the sync-on-green inputs (sogin0, sogin1) operate in two steps. first, they set a baseline clamp level off the incoming video signal with a negative peak detector. second, they set the voltage level of the sog slicers comparator (register 0x1d, bits[7:3]) with a variable trigger level to a programmable level (typically 128 mv) above the negative peak. each sync-on- green input must be ac-coupled to the green analog input through its own capacitor. the value of the capacitor must be 1 nf 20%. if sync-on-green is not used, this connection is not required. the sync-on-green signal always has negative polarity. r ain b ain g ain sogin 47nf 47nf 47nf 1nf 0 6476-004 figure 5. typical in put configuration reference bypassing reflo and refhi are connected to each other by a 10 f capacitor (see figure 6 ). these references are used by the input adc circuitry. refhi reflo 10f 0 6476-005 figure 6. input amplifier reference capacitors
ad9984a rev. 0 | page 14 of 44 clock generation a pll is used to generate the pixel clock. the hsync input provides a reference frequency to the pll. a voltage controlled oscillator (vco) generates a much higher pixel clock frequency. the pixel clock is divided by the pll divide value (register 0x01 and register 0x02) and phase-compared with the hsync input. any error is used to shift the vco frequency and maintain lock between the two signals. the stability of this clock is a very important element in provid- ing the clearest and most stable image. during each pixel time, the signal slews from the old pixel amplitude and settles at its new value; this is called the slewing time. then, the input voltage stabilizes before the signal must slew to a new value; this is called the stable time. the ratio of the slewing time to the stable time is a function of the graphics dac bandwidth and the bandwidth of the transmission system (cable and termination). this ratio is also a function of the overall pixel rate. if the dynamic charac- teristics of the system remain fixed, the slewing and settling time is likewise fixed. this ti me must be subtracted from the total pixel period, leaving the stable period. at higher pixel frequencies, the total cycle time is shorter and the stable pixel time becomes shorter as well. pixel cloc k in v alid sample times 0 6476-006 figure 7. pixel sampling times any jitter in the clock reduces the precision of the sampling time and it must also be subtracted from the stable pixel time. considerable care has been taken in the design of the ad9984a clock generation circuit to minimize jitter. the clock jitter of the ad9984a is low in all operating modes, making the reduction in the valid sampling time due to jitter negligible. the pll characteristics are determined by the loop filter design, the pll charge pump current, and the vco range setting. the loop filter design is illustrated in figure 8 . recommended settings of the vco range and charge pump current for vesa standard display modes are listed in table 10 . c p 8.2n f c z 82nf r z 1.5k ? filt pv d 06476-007 figure 8. pll loop filter design four programmable registers are provided to optimize the performance of the pll. these registers are the 12-bit divisor register, the 2-bit vco range register, the 3-bit charge pump current register, and the 5-bit phase adjust register. the 12-bit divisor register the input hsync frequencies can accommodate any hsync as long as the product of the hsync and the pll divisor falls within the operating range of the vco. the pll multiplies the frequency of the hsync signal, producing pixel clock frequencies in the range of 10 mhz to 170 mhz. the divisor register controls the exact multiplication factor. this register can be set to any value between 2 and 4095 as long as the output frequency is within range. the 2-bit vco range register to improve the noise performance of the ad9984a, the vco operating frequency range is divided into four overlapping regions. the vco range register sets this operating range. the frequency ranges for the four regions are shown in table 8 . table 8. vco frequency ranges pv1 pv0 pixel clock range (mhz) kvco gain (mhz/v) 0 0 10 to 31 1 150 0 1 31 to 62 150 1 0 62 to 124 150 1 1 124 to 170 150 1 for frequencies of 18 mhz or lower, enab le the vco low range bit (reg. 0x36[0]). the 3-bit charge pump current register this register varies the current that drives the low-pass loop filter. the possible current values are listed in table 9 . table 9. charge pump current/control bits ip2 ip1 ip0 current (a) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 the 5-bit phase adjust register the phase of the generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. the phase adjust register provides 32 phase-shift steps of 11.25 each. the hsync signal with an identical phase shift is available through the hsout pin. phase adjust is still available if an external pixel clock is used. the coast pin or the internal coast is used to allow the pll to continue to run at the same frequency in the absence of the incoming hsync signal or during disturbances in hsync (such as from equalization pulses). this can be used during the vertical sync period or at any other time that the hsync signal is unavailable.
ad9984a rev. 0 | page 15 of 44 the polarity of the coast signal can be set through the coast polarity register (register 0x18, bits[6:5]). in addition, the polarity of the hsync signal can be set through the hsync polarity register (register 0x12, bits[5:4]). for both hsync and coast, a value of 1 is active high. the internal coast function is driven off the vsync signal, which is typically a time when hsync signals can be disrupted with extra equalization pulses. table 10. recommended vco range and charge pump and current settings for standard display formats standard resolution refresh rate (hz) horizontal frequency (khz) pixel rate (mhz) pll divider vco range current vco gear (reg.0x36[0]) vga 640 480 60 31.500 25.175 800 00 101 0 72 37.700 31.500 832 01 100 0 75 37.500 31.500 840 01 100 0 85 43.300 36.000 832 01 100 0 svga 800 600 56 35.100 36.000 1024 01 100 0 60 37.900 40.000 1056 01 101 0 72 48.100 50.000 1040 01 101 0 75 46.900 49.500 1056 01 101 0 85 53.700 56.250 1048 01 110 0 xga 1024 768 60 48.400 65.000 1344 10 100 0 70 56.500 75.000 1328 10 101 0 75 60.000 78.750 1312 10 101 0 80 64.000 85.500 1336 10 101 0 85 68.300 94.500 1376 10 110 0 sxga 1280 1024 60 64.000 108.000 1688 10 110 0 75 80.000 135.000 1688 11 110 0 85 91.100 157.500 1728 11 110 0 uxga 1600 1200 60 75.000 162.000 2160 11 110 0 tv 480i 30 15.750 13.510 858 00 101 1 480p 60 31.470 27.000 858 00 101 0 576i 30 15.625 13.500 864 00 101 1 576p 60 31.250 27.000 864 00 101 0 720p 60 45.000 74.250 1650 10 101 0 1035i 30 33.750 74.250 2200 10 101 0 1080i 60 33.750 74.250 2200 10 101 0 1080p 60 67.500 148.500 2200 11 101 0
ad9984a rev. 0 | page 16 of 44 sync processing the inputs of the sync processing section of the ad9984a are combinations of digital hsyncs and vsyncs, analog sync-on- green or sync-on-y signals, and an optional external coast signal. from these signals, the part generates a precise, jitter- free clock from its pll, an odd/even-field signal, hsout and vsout signals, a count of hsyncs per vsync, and a programmable sogout. the main sync processing blocks are the sync slicer, sync separator, hsync filter, hsync regenerator, vsync filter, and coast generator. ? the sync slicer extracts the sync signal from the green graphics or luminance video si gnal that is connected to the soginx inputs, and outputs a digital composite sync. ? the sync separator extracts vsync from the composite sync signal, which can come from either the sync slicer or the hsyncx inputs. ? the hsync filter is used to eliminate any extraneous pulses from the hsyncx or soginx inputs, outputting a clean, low-jitter signal that is appropriate for mode detection and clock generation. ? the hsync regenerator is used to recreate a clean, although not low jitter, hsync signal that can be used for mode detection and counting hsyncs per vsync. ? the vsync filter is used to eliminate spurious vsyncs, main- tain a stable timing relationship between the vsync and hsync output signals, and generate the odd/even field output. ? the coast generator creates a robust coast signal to allow the pll to maintain its frequency in the absence of hsync pulses. ad9984a sogout hsync vsync coast coast select 0x18:7 datack sogin0 extck/coast vsync1 mux mux mux mux mux mux mux mux vsync0 hsync1 hsync0 hsout vsout/a0 sogin1 hsync select 0x12:6 filtered hsync activity detect activity detect activity detect activity detect activity detect activity detect polarity detect polarity detect polarity detect polarity detect sync slicer sync slicer pll clock generator o/e field channel select 0x1e:6 hsync filter and regenerator regenerated hsync set polarity sync processor and vsync filter 06476-008 set polarity hsync/vsync counter reg 0x26, 0x27 set polarity set polarity vsync filtered vsync vsync filter en 0x14:2 vsync filter en 0x14:2 pll sync filter en 0x20:2 sp sync filter en 0x20:1 sogout select 0x1d:1,0 mux figure 9. sync processing block diagram
ad9984a rev. 0 | page 17 of 44 sync slicer the purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the sog input. the sync signal is extracted in a two step process. first, the sog input is clamped to its negative peak, (typically 0.3 v below the black level). next, the signal goes to a comparator with a variable trigger level (set by register 0x1d, bits[7:3]), but nominally 0.128 v above the clamped level. the sync slicer output is a digital composite sync signal containing both hsync and vsync information (see figure 10 ). sync separator as part of sync processing, the sync separators task is to extract vsync from the composite sync signal. it works on the idea that the vsync signal stays active for a much longer time than the hsync signal. by using a digital low-pass filter and a digital comparator, the sync separator rejects pulses with small durations (such as hsyncs and equalization pulses) and only passes pulses with large durations, such as vsync (see figure 10 ). the threshold of the digital comparator is programmable for maximum flexibility. to program the threshold duration, write a value (n) to register 0x11. the resulting pulse width is n 200 ns. if, for example, n = 5, the digital comparator threshold is 1 s. any pulse less than 1 s is rejected, while any pulse greater than 1 s passes through. there are two factors to keep in mind when using the sync separator. first, the resulting clean vsync output is delayed from the original vsync by a duration equal to the digital comparator threshold ( n 200 ns). second, there is some variability to the 200 ns multiplier value. the maximum variability over all operating conditions is 20% (160 ns to 240 ns). because normal vsync and hsync pulse widths differ by a factor of approximately 500 or more, the 20% variability is not an issue. hsync filter and regenerator the hsync filter is used to eliminate any extraneous pulses from the hsync or sog inputs, outputting a clean, low jitter signal that is appropriate for mode detection and clock generation. the hsync regenerator is used to recreate a clean, but not low jitter, hsync signal that can be used for mode detection and counting hsyncs per vsync. the hsync regenerator has a high degree of tolerance to extraneous and missing pulses on the hsync input, but is not appropriate for use by the pll in creating the pixel clock due to jitter. the hsync regenerator runs automatically and requires no setup to operate. the hsync filter requires the setting up of a filter window. the filter window sets a periodic window of time around the regenerated hsync leading edge where valid hsyncs are allowed to occur. the general idea is that extraneous pulses on the sync input occur outside of this filter window and are thus, filtered out. to set the filter window timing, program a value ( x ) into register 0x23. the resulting filter window time is x times 25 ns around the regenerated hsync leading edge. just as for the sync separator threshold multiplier, allow a 20% variance in the 25 ns multiplier to account for all operating conditions (20 ns to 30 ns range). a second output from the hsync filter is a status bit (register 0x25, bit 1) that indicates if extraneous pulses are present on the incoming sync signal. extraneous pulses are often included for copy protection purposes, so this status bit can be used to detect such pulses. the filtered hsync (rather than the raw hsyncx/soginx signal) for pixel clock generation by the pll is controlled by register 0x20, bit 2. the regenerated hsync (rather than the raw hsyncx/soginx signal) for the sync processing is controlled by register 0x20, bit 1. using the filtered hsync and regenerated hsync is recommended. see figure 11 for an illustration of a filtered hsync. sog input sogout output connected to hsyncin negative pulse width = 40 sample clocks composite sync at hsyncin vsyncout from sync separator ?300mv +300mv 700mv maximum 0mv 06476-009 figure 10. sync slicer and sync separator output
ad9984a rev. 0 | page 18 of 44 hsyncout vsync filter window expected edge filter window equalization pulses hsyncin 06476-010 figure 11. sync processing filter vsync filter and odd/even fields the vsync filter is used to eliminate spurious vsyncs, maintain a stable timing relationship between the vsync and hsync output signals, and generate the odd/even field output. the filter works by examining the placement of vsync with respect to hsync and if necessary, shifting it in time slightly. the goal is to keep the vsync and hsync leading edges from switching at the same time, thus eliminating confusion as to when the first line of a frame occurs. register 0x14, bit 2 enables the vsync filter. use of the vsync filter is recommended for all cases, including interlaced video, and is required when using the hsyncs per vsync counter. figure 12 and figure 13 illustrate even/odd field determination in two situations. field 1 field 0 field 1 field 0 23 2 1 44 31 hsyncin vsyncin vsyncout o/e field even field quadrant 06476-012 sync seperator threshold figure 12. even field field 1 field 0 field 1 field 0 23 2 1 44 31 hsyncin vsyncin vsyncout o/e field odd field quadrant 06476-011 sync seperator threshold figure 13. odd field
ad9984a rev. 0 | page 19 of 44 power management to meet display requirements for low standby power, the ad9984a includes a power-down mode. the power-down state can be controlled manually (via pin 17 or register 0x1e, bit 3), or automatically by the chip. if automatic control is selected (register 0x1e, bit 4 =1), the ad9984as decision is based on the status of the following sync detect bits in register 0x24: bit 2, bit 3, bit 6, and bit 7. if either an hsync or a sync-on-green input is detected on any input, the chip powers up; otherwise, it powers down. for manual control, the ad9984a allows flexibility of control through both a dedicated pin and a register bit. for the dedicated pin, a hardware watchdog circuit controls power-down, while software controls power-down for the register bit. with manual power-down control, the polarity of the power-down pin must be set (register 0x1e, bit 2) whether the pin is used or not. if unused, it is recommended to set the polarity to active high and hardwire the pin to ground with a 10 k resistor. in power-down mode, several circuits continue to operate normally. the serial register and sync detect circuits maintain power so that the ad9984a can be woken up from its power- down state. the band gap circuit maintains power because it is needed for sync detection. the sync-on-green and sogout functions continue to operate because sogout is needed when sync detection is performed by a secondary chip. all of these circuits require minimal power to operate. typical standby power on the ad9984a is about 50 mw. there are two options that can be selected when in power- down. these are controlled by bit 0 and bit 1 in register 0x1e. bit 0 controls whether the sogout pin is in high impedance or not. in most cases, the user does not place sogout in high impedance during normal operation. the option to put sogout in high impedance is included mainly to allow for factory testing modes. bit 1 keeps the ad9984a powered up while placing only the outputs in high impedance. this option is useful when the data outputs from two chips are connected on a pcb and the user wants to switch instantaneously between the two. table 11.power-down control and mode descriptions inputs mode auto power-down control 1 power-down 2 sync detect 3 powered on/comments power-up 1 x 1 everything. power-down 1 x 0 only the serial bus, sync activity detect, sog, band gap reference. power-up 0 0 x everything. power-down 0 1 x only the serial bus, sync activity detect, sog, band gap reference. 1 auto power-down control is set by register 0x1e, bit 4. 2 power-down is controlled by oring pin 17 with register 0x1e, bit 3. the polarity of pin 17 is set by register 0x1e, bit 2. 3 sync detect is determined by oring regi ster 0x24, bit 2, bit 3, bit 6, and bit 7. timing diagrams the timing diagrams in figure 14 to figure 17 show the operation of the ad9984a. the output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. there is a pipeline in the ad9984a that must be flushed before valid data becomes available. this means six data sets are present before valid data is available. t per t dcycle t skew datack data hsout 06476-013 figure 14. output timing
ad9984a rev. 0 | page 20 of 44 datain p0 p1 p2 p5 p3 p4 p9 p6 p8 p10 p11 p7 hsyncx datack 8 clock cycle delay dataout p0 p1 p2 p3 2 clock cycle delay hsout 06476-014 figure 15. 4:4:4 timing mode datain hsyncx datack 8 clock cycle delay cb/crout yout 2 clock cycle delay hsout notes 1. pixel after hsout corresponds to blue input. 2. even number of pixel delay between hsout and dataout. p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 y0 cb0 cr0 cb2 cr2 y1 y2 y3 06476-015 figure 16. 4:2:2 timing mode datain p0 p1 p2 p5 p3 p4 p9 p6 p8 p10 p11 p7 hsyncx datac k 8 clock cycle delay 2 clock cycle delay ddr notes 1. output datack may be delayed 1/4 clock period in the registers. 2. see project document for values of f (falling edge) and r (rising edge). 3. for ddr 4:2:2 mode: timing is identical, values of f and r change. general notes 1. data delay may vary one clock cycle, depending on phase setting. 2. adcs sample input on falling edge of datack. 3. hsync shown is active high (edge shown is leading edge). hsout f0 r0 f1 r1 f2 r2 f3 r3 06476-016 figure 17. double data rate (ddr) timing mode hsync timing the hsync is processed in the ad9984a to eliminate ambiguity in the timing of the leading edge with respect to the phase- delayed pixel clock and data. the hsync input is used as a reference to generate the pixel sampling clock. the sampling phase can be adjusted with respect to hsync through a full 360 in 32 steps via the phase adjust register (to optimize the pixel sampling time). display systems use hsync to align memory and display write cycles. therefore, it is important to have a stable timing relationship between the hsync output (hsout) and data clock (datack). three things happen to hsync in the ad9984a. first, the polarity of hsync input is determined and, as a result, has a known output polarity. the known output polarity can be programmed either active high or active low (register 0x12, bit 3). second, hsout is aligned with datack and data outputs. third, the duration of hsout (in pixel clocks) is set via register 0x13. hsout is the sync signal that should be used to drive the rest of the display system.
ad9984a rev. 0 | page 21 of 44 coast timing in most computer systems, the hsync signal is provided continuously on a dedicated wire. in these systems, the coast input and function are unnecessary and should not be used. in some systems, however, hsync is disturbed during the vertical sync period (vsync). in some cases, hsync pulses disappear. in other systems, such as those that employ composite sync (csync) signals or embedded sync-on-green, hsync can include equalization pulses or other distortions during vsync. to avoid upsetting the clock generator during vsync, it is important to ignore these distortions. if the pixel clock pll sees extraneous pulses, it attempts to lock to this new frequency, and changes frequency by the end of the vsync period. it then takes a few lines of correct hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. the coast input is provided to eliminate this problem. it is an asynchronous input that disables the pll input and holds the clock at its current frequency. the pll can free run for several lines without significant frequency drift. coast can be generated internally by the ad9984a (see register 0x18) or can be provided externally by the graphics controller. when internal coast is selected (register 0x18, bit 7 = 0, and register 0x14, bits[7:6] to select source), vsync is used as a basis for determining the position of coast. the internal coast signal is enabled a programmed number of hsync periods before the periodic vsync signal (precoast register 0x16), and it is dropped a programmed number of hsync periods after vsync (postcoast register 0x17). it is recommended that the vsync filter be enabled when using the internal coast function to allow the ad9984a to precisely determine the number of hsyncs/vsync and their location. in many applications where disruptions occur and coast is used, values of 2 for precoast and 10d for postcoast are sufficient to avoid most extraneous pulses. output formatter the output formatter is capable of generating several output formats to be presented to the 30 data output pins. the output formats and the pin assignments for each format are listed in table 12 . in addition, there are several clock options for the output clock. the user can select the pixel clock, a 90 phase- shifted pixel clock, a 2 pixel clock, or a 0.5 pixel clock for test purposes. the output clock can also be inverted. data output is available as 30-pin rgb or ycbcr, or, if either 4:2:2 or 4:4:4 ddr is selected, a secondary channel is available. this secondary channel is always 4:2:2 ddr. it contains the same video data as the primary channel and can be utilized by either another display or storage device. depending on the choice of output modes, the primary output can be 30 pins, 20 pins, or as few as 15 pins. mode descriptions 4:4:4 all channels come out with their 10 data bits at the same time. data is aligned to the negative edge of the clock for easy capture. this is the normal 30-bit output mode for rgb or 4:4:4 ycbcr. 4:2:2 red and green channels contain 4:2:2 formatted data (20 pins) with y data on the green channel and cb, cr data on the red channel. data is aligned to the negative edge of the clock. the blue channel contains the secondary channel with cb, y, cr, y formatted 4:2:2 ddr data. the data edges are aligned to both edges of the pixel clock, therefore, using a 90 clock may be necessary to capture the ddr data. 4:4:4 ddr this mode puts out full 4:4:4 data on 15 bits of the red and green channels, thus saving 15 pins. the first half (rgb[14:0]) of the 30-bit data is sent on the rising edge and the second half (rgb[29:15]) is sent on the falling edge. ddr 4:2:2 data is sent on the blue channel, as in 4:2:2 mode. rgb[29:0] = r[9:0] + g[9:0] + b[9:0], so rgb[29:15] = r[9:0] + g[9:5] and rgb[14:0] = g[4:0] + b[9:0] table 12. output formats 1 port red green blue bit 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 4:4:4 red/cr green/y blue/cb 4:2:2 2 cb, cr y ddr 4:2:2 cb,cr y,y ddr g[4:0] ddr b[9:0] n/a ddr 4:2:2 cb,cr 4:4:4 ddr ddr r[9:0] ddr g[9:5] n/a ddr 4:2:2 y,y 1 arrows in table indicate clock edge. rising edge of clock = , falling edge = . 2 for 4:2:2 modes, cb is sent before cr.
ad9984a rev. 0 | page 22 of 44 2-wire serial control port a 2-wire serial control interface is provided with the ad9984a. up to two ad9984a devices can be connected to the 2-wire serial interface with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bi- directional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. the following are the five components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high), communication is initiated by sending a start signal. the start signal is a high-to-low transiti on on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the first 8 bits of data transferred after a start signal comprise a 7-bit slave address (the first seven bits) and a single r/ w bit (the eighth bit). the r/ w bit indicates the direction of data transfer, read from 1 or write to 0 on the slave device. if the transmitted slave address matches the address of the device, the ad9984a acknowledges the match by bringing sda low on the ninth scl pulse. if the addresses do not match, the ad9984a does not acknowledge it. table 13. serial port addresses bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a6 (msb) a5 a4 a3 a2 a1 a0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 data transfer via serial interface for each byte of data read or written, the msb is the first bit in the sequence. if the ad9984a does not acknowledge the master device during a write sequence, the sda remains high so the master can generate a stop signal. if the master device does not acknowledge the ad9984a during a read sequence, the ad9984a interprets this as end of data. the sda remains high so the master can generate a stop signal. writing data to specific control registers of the ad9984a requires writing to the 8-bit address of the control register of interest after the slave address has been established. this control register address is the base address for subsequent write operations. after the initial data byte is written, the base address auto- increments by one for each additional data byte. if more bytes are transferred than available addresses, the address does not increment and remains at its maximum value of 0x44. any base address higher than 0x44 does not produce an acknowledge signal. data is read from the control registers of the ad9984a in a similar manner. reading requires two data transfer operations. ? the base address must be written with the r/ w bit of the slave address byte low to set up a sequential read operation. reading (the r/ w bit of the slave address byte high) begins at the previously established base address. the address of the read register auto-increments after each byte is transferred. ? to terminate a read/write sequence to the ad9984a, a stop signal must be sent. a stop signal comprises a low-to-high transition of sda while scl is high. a repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. s d a scl t buff t s t a h t dho t dsu t dal t dah t stasu t stosu 06476-017 figure 18. serial port read/write timing
ad9984a rev. 0 | page 23 of 44 serial interface read/write examples write to one control register 1. start signal 2. slave address byte (r/ w bit = low) 3. base address byte 4. data byte to base address 5. stop signal write to four consecutive control registers 1. start signal 2. slave address byte (r/ w bit = low) 3. base address byte 4. data byte to base address 5. data byte to (base address + 1) 6. data byte to (base address + 2) 7. data byte to (base address + 3) 8. stop signal read from one control register 1. start signal 2. slave address byte (r/ w bit = low) 3. base address byte 4. start signal 5. slave address byte (r/ w bit = high) 6. data byte from base address 7. stop signal read from four consecutive control registers 1. start signal 2. slave address byte (r/ w bit = low) 3. base address byte 4. start signal 5. slave address byte (r/ w bit = high) 6. data byte from base address 7. data byte from (base address + 1) 8. data byte from (base address + 2) 9. data byte from (base address + 3) 10. stop signal bit 7 ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sda scl 06476-018 figure 19. serial interfacetypical byte transfer
ad9984a rev. 0 | page 24 of 44 2-wire serial register map the ad9984a is initialized and controlled by a set of registers that determine the operating modes. an external controller is e mployed to write and read the control registers through the 2-wire serial interface port. table 14. control register map hex address read/write, read only bits default value register name description 0x00 ro 7:0 0010 0000 chip revision an 8-bit register that represents the silicon revision level. 0x01 r/ w 7:0 0110 1001 pll div msbs the 8 msbs (bits[11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded first when a change is needed. (this gives the pll more time to lock). 1 0x02 r/ w 7:4 1101 **** pll div lsbs the 4 lsbs (bits[3:0]) of the pll divider. links to the pll div msb to make a 12-bit register. 1 0x03 r/ w 7:6 01** **** vco/cpmp vco range select. chooses the vco frequency range (see the clock generation section). 5:3 **00 1*** charge pump current. varies the current that drives the low-pass filter (see the clock generation section). 2 **** *0** external clock enable. 0x04 r/ w 7:3 1000 0*** phase adjust adc clock phase adjust. larger values mean more delay. (1 lsb = t/32). 0x05 r/ w 6:0 *100 0000 red gain msbs the 7 msbs of the red channel gain control. controls adc input range (contrast) of each respective channel. larger values give less contrast. 0x06 r/ w 7:6 00** **** red gain lsbs the 2 lsbs of the red channel gain control. links with register 0x05 to form the 9-bit red gain that controls the adc input range (contrast) of the red channel. a lower value corresponds to a higher gain. 1 0x07 r/ w 6:0 *100 0000 green gain msbs the 7 msbs of the green channel gain control. controls adc input range (contrast) of each respective channel. larger values give less contrast. 0x08 r/ w 7:6 00** **** green gain lsbs the 2 lsbs of the green channel gain control. links to register 0x07 to form the 9-bit green gain that controls the adc input range (contrast) of the green channel. a lower value corresponds to a higher gain. 1 0x09 r/ w 6:0 *100 0000 blue gain msbs the 7 msbs of the blue channel gain control. controls adc input range (contrast) of each respective channel. larger values give less contrast. 0x0a r/ w 7:6 00** **** blue gain lsbs the 2 lsbs of the blue channel gain control. links to register 0x09 to form the 9-bit blue gain that co ntrols the adc input range (contrast) of the blue channel. a lower value corresponds to a higher gain. 1 0x0b r/ w 7:0 0100 0000 red offset msbs the 8 msbs of the red channel offset control. controls dc offset (brightness) of each respective channel. larger values decrease brightness. 1 0x0c r/ w 7:5 000* **** red offset lsbs the 3 lsbs of the red channel offset control. links to register 0x0b to form the 11-bit red offset that controls the dc offset (brightness) of the red channel in auto-offset mode. 0x0d r/ w 7:0 0100 0000 green offset msbs the 8 msbs of the green channel offset control. controls dc offset (brightness) of each respective channel. larger values decrease brightness. 1 0x0e r/ w 7:5 000* **** green offset lsbs the 3 lsbs of the green channel offset control. links to register 0x0d to form the 11-bit green offset that controls the dc offset (brightness) of the green channel in auto-offset mode. 0x0f r/ w 7:0 0100 0000 blue offset msbs the 8 msbs of the blue channel offset control. controls dc offset (brightness) of each respective channel. larger values decrease brightness. 1 0x10 r/ w 7:5 000* **** blue offset lsbs the 3 lsbs of the blue channel offset control. links to register 0x0f to form the 11-bit blue offset that controls the dc offset (brightness) of the blue channel in auto-offset mode. 0x11 r/ w 7:0 0010 0000 sync separator threshold sets the threshold of the sync separators digital comparator. 0x12 r/ w 7 0*** **** hsync control hsync source override. 0 = the chip determines the active hsync source. 1 = the active hsync source is set by reg. 0x12, bit 6.
ad9984a rev. 0 | page 25 of 44 hex address read/write, read only bits default value register name description 6 *0** **** hsync source select. determines the source of the hsync for pll and sync processing. this bit is used only if reg. 0x12, bit 7 is set to 1 or if both syncs are active. 0 = hsync is from hsyncx input pin. 1 = hsync is from sog. 5 **0* **** hsync input polarity override. 0 = the chip selects the hsync input polarity. 1 = the input polarity of hsync is controlled by reg. 0x12, bit 4. 4 ***1 **** hsync input polarity. this bit is used on ly if reg. 0x12, bit 5 is set to 1. 0 = hsync input polarity is negative. 1 = hsync input polarity is positive. 3 **** 1*** hsync output polarity. sets the pol arity of the hsync output signal (hsout). 0 = hsout polarity is negative. 1 = hsout polarity is positive. 0x13 r/ w 7:0 0010 0000 hsync duration sets the number of pixel clocks that hsout is active. 0x14 r/ w 7 0*** **** vsync control vsync source override. 0 = the chip determines the active vsync source. 1 = the active vsync source is set by reg. 0x14, bit 6. 6 *0** **** vsync source select. determines the source of vsync for sync processing. this bit is used only if reg. 0x14, bit 7 is set to 1. 0 = vsync is from the vsyncx input pin. 1 = vsync is from the sync separator. 5 **0* **** vsync input polarity override. 0 = the chip selects vsync input polarity. 1 = the input polarity of vsync is set by reg. 0x14, bit 4. 4 ***1 **** vsync input polarity. this bit is used on ly if reg. 0x14, bit 5 is set to 1. 0 = vsync input polarity is negative. 1 = vsync input polarity is positive. 3 **** 1*** vsync output polarity. sets the polarity of the output vsync signal (vsout). 0 = vsout polarity is negative. 1 = vsout polarity is positive. 2 **** *0** vsync filter enable. this needs to be enabled when using the hsync to vsync counter. 0 = the vsync filter is disabled. 1 = the vsync filter is enabled. 1 **** **0* vsync duration block enable. this is designed to be used with the vsync filter. 0 = vsync output duration is unchanged. 1 = vsync output duration is set by register 0x15. 0x15 r/ w 7:0 0000 1010 vsync duration sets the number of hsyncs that vsync out is active. this is only used if reg. 0x14, bit 1 is set to 1. 0x16 r/ w 7:0 0000 0000 precoast the number of hsync periods to coast prior to vsync. 0x17 r/ w 7:0 0000 0000 postcoast the number of hsync periods to coast after vsync. 0x18 r/ w 7 0*** **** coast and clamp control coast source. determines the source of the coast signal. 0 = using internal coast generated from vsync. 1 = using external coast signal from coast pin. 6 *0** **** coast polarity override. 0 = the chip selects the coast polarity. 1 = the polarity of the coast sign al is set by reg. 0x18, bit 5. 5 **1* **** coast polarity. this bit is used only if reg. 0x18, bit 6 is set to 1. 0 = coast polarity is negative. 1 = coast polarity is positive. 4 ***0 **** clamp source select. determines the source of the clamp timing. 0 = uses the internal clamp generated from hsync. 1 = uses the external clamp signal.
ad9984a rev. 0 | page 26 of 44 hex address read/write, read only bits default value register name description 3 **** 0*** red clamp select. 0 = clamp the red channel to ground. 1 = clamp the red channel to midscale. 2 **** *0** green clamp select. 0 = clamp the green channel to ground. 1 = clamp the green channel to midscale. 1 **** **0* blue clamp select. 0 = clamp the blue channel to ground. 1 = clamp the blue channel to midscale. 0 **** ***0 must be set to 0 for proper operation. 0x19 r/ w 7:0 0000 1000 clamp placement places the clamp signal an integer number of clock periods after the trailing edge of the hsync signal. 0x1a r/ w 7:0 0010 0000 clamp duration number of clock periods that the clamp signal is actively clamping. 0x1b r/ w 7 0*** **** clamp and offset clamp polarity override. 0 = the chip selects the clamp polarity. 1 = the polarity of the clamp signal is set by reg. 0x1b, bit 6. 6 *1** **** clamp polarity. this bit is used only if reg. 0x1b, bit 7 is set to 1. 0 = clamp polarity is negative. 1 = clamp polarity is positive. 5 **0* **** auto-offset enable. 0 = auto-offset is disabled. 1 = auto-offset is enabled (offsets become the desired clamp code). 4:3 ***1 1*** auto-offset update frequency. this selects how often the auto- offset circuit operates. 00 = every 3 clamps. 01 = every 48 clamps. 10 = every 192 clamps. 11 = every 3 vsync periods. 2:0 **** *011 must be written to default (011) for proper operation. 0x1c r/ w 7:0 1111 1111 test register 0 must be set to 0xff for proper operation. 0x1d r/ w 7:3 0111 1*** sog control sog slicer comparator threshold. sets the voltage level of sog slicers comparator. 2 **** *0** sogout polarity. sets the polarity of the signal on the sogout pin. 0 = sogout polarity is negative. 1 = sogout polarity is positive. 1:0 **** **00 sogout select. 00 = raw soginx. 01 = raw hsyncx. 10 = regenerated hsync from sync filter. 11 = filtered hsync from sync filter. 0x1e r/ w 7 *** **** input and power control channel select override. 0 = the chip determines which input channels to use. 1 = the input channel selection is determined by reg. 0x1e, bit 6. 6 *0** **** channel select. this is used only if reg. 0x1e, bit 7 is set to 1, or if syncs are present on both channels. 0 = channel 0 syncs and data are selected. 1 = channel 1 syncs and data are selected. 5 **1* **** programmable bandwidth. 0 = low analog input bandwidth (~7 mhz). 1 = high analog input bandwidth (~300 mhz). 4 ***1 **** power-down control select. 0 = manual power-down control. 1 = auto power-down control. 3 **** 0*** power-down. 0 = normal operation. 1 = power-down.
ad9984a rev. 0 | page 27 of 44 hex address read/write, read only bits default value register name description 2 **** *0** power-down pin polarity. sets th e polarity of the signal on the pwrdn pin. 0 = pwrdn polarity is negative. 1 = pwrdn polarity is positive. 1 **** **0* power-down fast switching control. 0 = normal power-down operation. 1 = the chip stays powered up, and the outputs are put in high impedance mode. 0 **** ***0 sogout high impedance control. 0 = sogout operates as normal during power-down. 1 = sogout is in high impedance during power-down. 0x1f r/ w 7:5 100* **** output select 1 output mode. 100 = 4:4:4 rgb mode. 101 = 4:2:2 ycbcr mode. 110 = 4:4:4 ddr mode. 4 ***1 **** primary output enable. 0 = primary output is in high impedance state. 1 = primary output is enabled. 3 **** 0*** secondary output enable. 0 = secondary output is in high impedance state. 1 = secondary output is enabled. 2:1 **** *10* output drive strength. applies to all outputs except vsout. 00 = low output drive strength. 01 = medium output drive strength. 1x = high output drive strength. 0 **** ***0 output clock invert. applies to all clocks output on datack. 0 = noninverted pixel clock. 1 = inverted pixel clock. 0x20 r/ w 7:6 0*** **** output select 2 output clock select. 00 = pixel clock. 01 = 90 phase-shifted pixel clock. 10 = 2 pixel clock. 11 = 0.5 pixel clock. 5 *0** **** output high impedance. 0 = normal outputs. 1 = all outputs except sogout in high impedance mode. 4 **0* **** sogout high impedance. 0 = normal drive. 1 = sogout pin is in high impedance mode. 3 ***0 **** field output polarity. sets the pol arity of the field output signal. 0 = active low is an even field, active high is an odd field. 1 = active low is an odd field, active high is an even field. 2 **** 1*** pll sync filter enable. 0 = pll uses raw hsyncx/soginx. 1 = pll uses filtered hsync/sog. 1 **** *0** sync processing input select. selects the sync source for the sync processor. 0 = sync processing uses raw hsyncx/soginx. 1 = sync processing uses regenerated hsync from sync filter. 0 **** ***0 must be set to 1 for proper operation. 0x21 r/ w 7:0 0010 0000 must be set to default for proper operation. 0x22 r/ w 7:0 0011 0010 must be set to default for proper operation. 0x23 r/ w 7:0 0000 1010 sync filter window width sets the window of time around the regenerated hsync leading edge (in 25 ns steps) that sync pulses are allowed to pass through. 0x24 ro 7 _*** **** sync detect hsync0 detection. 0 = hsync0 is not active. 1 = hsync0 is active.
ad9984a rev. 0 | page 28 of 44 hex address read/write, read only bits default value register name description 6 *_** **** hsync1 detection. 0 = hsync1 is not active. 1 = hsync1 is active. 5 **_* **** vsync0 detection. 0 = vsync0 is not active. 1 = vsync0 is active. 4 ***_ **** vsync1 detection. 0 = vsync1 is not active. 1 = vsync1 is active. 3 **** _*** sogin0 detection. 0 = sogin0 is not active. 1 = sogin0 is active. 2 **** *_** sogin1 detection. 0 = sogin1 is not active. 1 = sogin1 is active. 1 **** **_* coast detection. 0 = external coast is not active. 1 = external coast is active. 0 **** ***_ clamp detection. 0 = external clamp is not active. 1 = external clamp is active. 0x25 ro 7 _*** **** sync polarity detect hsync0 polarity. 0 = hsync0 polarity is negative. 1 = hsync0 polarity is positive. 6 *_** **** hsync1 polarity. 0 = hsync1 polarity is negative. 1 = hsync1 polarity is active high. 5 **_* **** vsync0 polarity. 0 = vsync0 polarity is negative. 1 = vsync0 polarity is positive. 4 ***_ **** vsync1 polarity. 0 = vsync1 polarity is negative. 1 = vsync1 polarity is positive. 3 **** _*** coast polarity. 0 = external coast is negative. 1 = external coast is positive. 2 **** *_** clamp polarity. 0 = external clamp is negative. 1 = external clamp polarity is positive. 1 **** **_* extraneous pulse detection. 0 = no extraneous pulses detected on hsync. 1 = extraneous pulses detected on hsync. 0 **** ***_ sync filter lock. 0 = sync filter unlocked 1 = sync filter locked. 0x26 ro 7:0 hsyncs per vsync msbs msbs of hsyncs per vsync count. 0x27 ro 7:4 hsyncs per vsync lsbs lsbs of hsyncs per vsync count. 0x28 r/ w 7:0 1011 1111 test register 1 must be written to 0xbf for proper operation. 0x29 r/ w 7:0 0000 0010 test register 2 must be written to 0x02 for proper operation. 0x2a ro 7:0 test register 3 read only bits for future use. 0x2b ro 7:0 test register 4 read only bits for future use. 0x2c r/ w 7:5 000* **** offset hold must be writ ten to default for proper operation.
ad9984a rev. 0 | page 29 of 44 hex address read/write, read only bits default value register name description 4 ***0 **** auto-offset hold. disables the auto-offset and holds the feedback result. 0 = continuous update. 1 = one time update. 3:0 **** 0000 must be written to default for proper operation. 0x2d r/ w 7:0 1111 0000 test register 5 must be written to 0xe8 for proper operation. 0x2e r/ w 7:0 1111 0000 test register 6 must be written to 0xe0 for proper operation. 0x34 r/ w 2 **** *0** sog filter sog filter enable. when enabled, filters out sog inputs less than 250 ns. 0 = sog filter disabled. 1 = sog filter enabled. 0x36 r/ w 0 **** ***0 vco gear vco gear select. adds another range to the vco. used for lower frequencies only. 0 = disable low vco gear. 1 = enable low vco gear. 0x3c r/ w 7:4 0000 **** auto gain test bits. must be set to default for proper operation. 3 **** 0*** auto gain matching hold. 0 = disables auto gain updates and ho lds the current auto offset values. 1 = allows auto gain to continuously update. 2:0 **** *000 auto gain matching enable. 000 = auto gain matching is disabled. 110= auto gain matching is enabled. 1 functions with more than eight control bits, such as pll divide ratio, gain, and offset, are only updated when the lsbs are wr itten to (for example, register 0x02 for pll divide ratio).
ad9984a rev. 0 | page 30 of 44 2-wire serial control registers chip identification 0x00bits[7:0] chip revision this is an 8-bit register that represents the silicon revision . pll divider control 0x01bits[7:0] pll divide ratio msbs these are the 8 msbs of the 12-bit pll divide ratio (plldiv). the pll derives a pixel clock from the incoming hsync signal. the pixel clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 2 to 4095 as long as the output frequency is within range. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed hsync frequency. vesa has established some standard timing specifications that assist in determining the value for plldiv as a function of horizontal and vertical display resolution and frame rate (see table 10 ). however, many computer systems do not precisely conform to the recommendations. as a result, these numbers should be used only as a guide. the display system manufac- turer should provide automatic or manual means for optimizing plldiv. an incorrectly set plldiv usually produces one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default value of plldiv is 1693. plldivm = 0x69, plldivl = 0xdx. the ad9984a updates the full divide ratio only when the lsbs are written. writing to this register by itself does not trigger an update. 0x02bits[7:4] pll divide ratio lsbs these are the four lsbs of the 12-bit pll divide ratio (plldiv). the power-up default value of plldiv is 1693. plldivm = 0x69, plldivl = 0xdx. clock generator control 0x03bits[7:6] vco range select these two bits establish the operating range of the clock generator. vco range must be set to correspond to the desired operating frequency (incoming pixel rate). the pll gives the best jitter performance at high frequencies. for this reason, to output low pixel rates and still achieve good jitter performance, the pll operates at a higher frequency, but then divides down the clock rate afterwards. see table 15 for the pixel rates of each vco range setting. the pll output divisor is automatically selected with the vco range setting. the power-up default value is 01. table 15. vco range select bits value result (pixel rates) 00 10 to 31 01 31 to 62 10 62 to 124 11 124 to 170 0x03bits[5:3] charge pump current these three bits establish the current driving the loop filter in the clock generator. the current must be set to correspond with the desired operating frequency. the power-up default value is current = 001. table 16. charge pump current bits ip2 ip1 ip0 result (current) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 0x03bit[2] extern al clock enable this bit determines the source of the pixel clock. table 17. external clock enable bit value result 0 internally generated clock. 1 externally provided clock signal. a logic 0 enables the internal pll that generates the pixel clock from an externally provided hsync. a logic 1 enables the external extck input pin. in this mode, the pll divide ratio (plldiv) is ignored. the clock phase adjust (phase) is still functional. the power-up default value is extck = 0. phase adjust 0x04bits[7:3] adc clock phase adjust these bits adjust the phase for the dll to generate the adc clock. the 5-bit value adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 shift in sampling phase. the power-up default is 16. input gain the ad9984a can accommodate input signals with a full-scale range between 0.5 v and 1.0 v p-p. setting the red, green, or blue channel gain to 511 corresponds to an input range of 1.0 v. a red, green, or blue channel gain of 0 establishes an input range of 0.5 v. note that increasing gain results in the picture having less contrast (the input signal uses fewer available converter codes).
ad9984a rev. 0 | page 31 of 44 0x05bits[6:0] red channel gain control msbs this register contains the 7-bit msbs of the red channel gain control. values written to this register are not updated until the lsb register (register 0x06) has also been written to. the power-up default is 1000000. 0x06 bits[7:6] red channel gain control lsbs this register contains the 2-bit lsbs of the red channel gain control. along with the 7 msbs of gain control in register 0x05, there are 9 bits of gain control. default power-up value is 00. 0x07bits[6:0] green chan nel gain control msbs this register contains the 7-bit msbs of the green channel gain control. register update requires writing 0x00 to register 0x08. 0x08bits[7:6] green chan nel gain control lsbs this register contains the 2-bit lsbs of the green channel gain control. along with the 7 msbs of gain control in register 0x07, there are 9 bits of gain control. default power-up value is 00. 0x09bits[6:0] blue channel gain control msbs this register contains the 7-bit msbs of the blue channel gain control. register update requires writing 0x00 to register 0x0a. 0x0abits[7:6] blue channel gain control lsbs this register contains the 2-bit lsbs of the blue channel gain control. along with the 7 msbs of gain control in register 0x09, there are 9 bits of gain control. default power-up value is 00. input offset the offset control shifts the analog input, resulting in a change in brightness. note that the function of the red, blue, or green channel offset registers depends on whether auto-offset is enabled (register 0x1b, bit 5). if auto-offset is disabled, nine bits of the offset registers (bits[6:0] of the offset msb register plus bits[7:6] of the following register) control the absolute offset added to the channel (for the red channel, register 0x0b, bits[6:0] plus register 0x0c, bits[7:6]) control the absolute offset added to the channel. the offset control provides a 255 lsbs of adjustment range, with 1 lsb of offset corresponding to 1 lsb of output code. if auto-offset is enabled, the 11-bit offset (comprised of the 8 bits of the msb register and bits[7:5] of the following lsb register) determines the clamp target code. the 11-bit offset consists of 1 sign bit plus 10 bits. if the register is programmed to 530d, the output code is equal to 530d at the end of the clamp period. note that incrementing the offset register setting by 1 lsb adds 1 lsb of offset, regardless of the auto-offset setting. 0x0bbits[7:0] red channe l offset control msbs this register is the 8-bit msbs of the red channel offset control. along with the 3 lsbs in the red channel offset in register 0x0c, there are 11 bits of dc offset control in the red channel. values written to this register are not updated until the lsb register (register 0x0c) has also been written to. 0x0cbits[7:5] red channe l offset control lsbs this register contains the 3-bit lsbs of the red channel offset control. combining these bits with the 8 bits of msbs in register 0x0b creates 11 bits of offset control. 0x0dbits[7:0] green chan nel offset control msbs this register contains the 8-bit msbs of the green channel offset control. update of this register occurs only when register 0x0e is also written to. 0x0ebits[7:5] green chan nel offset control lsbs this register contains the 3-bit lsbs of the green channel offset control. combining these bits with the 8 bits of msbs in the register 0x0d makes 11 bits of offset control. 0x0fbits[7:0] blue chan nel offset control msbs the 8-bit blue channel offset control. update of this register occurs only when register 0x10 is also written to. 0x10bits[7:5] blue channel offset control lsbs the lsbs of the blue channel offset control combine with the 8 bits of msbs in the register 0x0f to make 11 bits of offset control. hsync control 0x11bits[7:0] sync separator threshold this register sets the threshold of the sync separators digital comparator. the value written to this register is multiplied by 200 ns to get the threshold value. therefore, if a value of 5 is written, the digital comparator threshold is 1 s and any pulses less than 1 s are rejected by the sync separator. there is some variability to the 200 ns multiplier value. the maximum variability over all operating conditions is 20% (160 ns to 240 ns). because normal vsync and hsync pulse widths differ by a factor of about 500 or more, the 20% variability is not an issue. the power-up default value is 32d. 0x12bit[7] hsync source override this bit is the hsync source override. setting this bit to 0 allows the chip to determine the active hsync source. setting it to 1 uses bit 6 of register 0x12 to determine the active hsync source. power-up default value is 0. table 18. hsync source override bit value result 0 hsync source determined by chip. 1 hsync source determined by user (register 0x12, bit 6). 0x12bit[6] hsync source select this bit selects the source of the hsync for pll and sync processing (only if bit 7 of register 0x12 is set to 1 or if both syncs are active). setting this bit to 0 specifies the hsync from the input pin. setting it to 1 selects hsync from sog. power-up default is 0. table 19. hsync source select bit value result 0 hsyncx input. 1 hsync from sog.
ad9984a rev. 0 | page 32 of 44 0x12bit[5] hsync input polarity override this bit determines whether the chip selects the hsync input polarity or if it is specified. setting this bit to 0 allows the chip to automatically select the polarity of the input hsync. setting it to 1 indicates that bit 4 of register 0x12 specifies the polarity. power-up default is 0. table 20. hsync input polarity override bit value result 0 hsync polarity determined by chip. 1 hsync polarity determined by user (register 0x12, bit 4). 0x12bit[4] hsync input polarity if bit 5 of register 0x12 is 1, the value of this bit specifies the polarity of the input hsync. setting this bit to 0 indicates a negative hsync input polarity. setting this bit to 1 indicates a positive hsync input polarity. power-up default is 1. table 21. hsync input polarity bit value result 0 hsync input polarity is negative. 1 hsync input polarity is positive. 0x12bit[3] hsync output polarity this bit sets the polarity of the hsync output (hsout). setting this bit to 0 indicates a negative hsout polarity. setting this bit to 1 indicates a positive hsout polarity. table 22. hsync output polarity bit value result 0 hsout polarity is negative. 1 hsout polarity is positive. 0x13bits[7:0] hsync duration this 8-bit register sets the duration of the hsout pulse. the leading edge of the hsync output is triggered by the internally generated, phase-adjusted, pll feedback clock. the ad9984a then counts a number of pixel clocks equal to the value in this register. this triggers the trailing edge of hsout, which is also phase-adjusted. vsync control 0x14bit[7] vsync source override this bit is the active vsync override. setting this to 0 allows the chip to determine the active vsync source, setting it to 1 uses bit 6 of register 0x14 to determine the active vsync source. power-up default value is 0. table 23. vsync source override bit value result 0 vsync source determined by chip. 1 vsync source determined by user (register 0x14, bit 6). 0x14bit[6] vsync source select this bit selects the source of the vsync for sync processing only if bit 7 of register 0x14 is set to 1. setting bit 6 to 0 specifies the vsync from the input pin. setting it to 1 selects vsync from the sync separator. power-up default is 0. table 24. vsync source select bit value result 0 vsync from vsyncx input pin. 1 vsync from sync separator. 0x14bit[5] vsync input polarity override this bit sets whether the chip selects the vsync input polarity or if it is specified. setting this bit to 0 allows the chip to automatically select the polarity of the input vsync. setting this bit to 1 indicates that bit 4 of register 0x14 specifies the polarity. power-up default is 0. table 25. vsync input polarity override bit value result 0 vsync polarity determined by chip. 1 vsync polarity determined by user (register 0x14, bit 4). 0x14bit[4] vsync input polarity if bit 5 of register 0x14 is 1, the value of this bit specifies the polarity of the input vsync. setting this bit to 0 indicates a negative vsync input polarity. setting this bit to 1 indicates a positive vsync input polarity. power-up default is 1. table 26. vsync input polarity bit value result 0 vsync input polarity is negative. 1 vsync input polarity is positive. 0x14bit[3] vsync output polarity this bit sets the polarity of the vsync output (vsout). setting this bit to 0 indicates a negative vsout polarity. setting this bit to 1 indicates a positive vsout polarity. power-up default is 1. table 27. vsync output polarity bit value result 0 vsout polarity is negative. 1 vsout polarity is positive. 0x14bit[2] vsync filter enable this bit enables the vsync filter allowing precise placement of the vsync with respect to the hsync and facilitating the correct operation of the hsyncs/vsync count. table 28. vsync filter enable bit value result 0 vsync filter disabled. 1 vsync filter enabled.
ad9984a rev. 0 | page 33 of 44 0x14bit[1] vsync duration block enable this enables the vsync duration block, which is designed to be used with the vsync filter. setting the bit to 0 leaves the vsync output duration unchanged. setting the bit to 1 sets the vsync output duration based on register 0x15. power-up duration is 0. table 29. vsync duration block enable bit value result 0 vsync output duration is unchanged. 1 vsync output duration is set by register 0x15. 0x15bits[7:0] vsync duration this register is used to set the output duration of the vsync, and is designed to be used with the vsync filter. this is valid only if register 0x14, bit 1 is set to 1. power-up default is 10d. coast and clamp controls 0x16bits[7:0] precoast this register allows the internally generated coast signal to be applied prior to the vsync signal. this is necessary in cases where pre-equalization pulses are present. the step size for this control is one hsync period. for precoast to work correctly, it is necessary for both the vsync filter (register 0x14, bit 2) and sync processing filter (register 0x20, bit 1) to either be enabled or disabled. the power-up default is 00. 0x17bits[7:0] postcoast this register allows the internally generated coast signal to be applied following the vsync signal. this is necessary in cases where post equalization pulses are present. the step size for this control is one hsync period. for postcoast to work correctly, it is necessary for both the vsync filter (register 0x14, bit 2) and sync processing filter (register 0x20, bit 1) to be enabled or disabled. the power-up default is 00. 0x18bit[7] coast source this bit is used to select the active coast source. the choices are the coast input pin or vsync. if vsync is selected, the addi- tional decision of using the vsyncx input pin or the output from the sync separator needs to be made (register 0x14, bits[7:6]). table 30. coast source bit value result 0 vsync (internal coast). 1 coast pin. 0x18bit[6] coast polarity override this register is used to override the internal circuitry that determines the polarity of the coast signal going into the pll. the power-up default setting is 0. table 31. coast polarity override bit value result 0 coast polarity determined by chip. 1 coast polarity determined by user (register 0x18, bit 5). 0x18bit[5] input coast polarity this register sets the input coast polarity when bit 6 of register 0x18 is 1. the power-up default setting is 1. table 32. input coast polarity bit value result 0 coast polarity is negative. 1 coast polarity is positive. 0x18bit[4] clamp source select this bit determines the source of clamp timing. a 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. the clamp position and duration is counted from the leading edge of hsync. a 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clamp polarity bit. the power-up default setting is 0. table 33. clamp source select bit value result 0 internally generated clamp. 1 externally provided clamp signal (clamp). 0x18bit[3] red clamp select this bit determines whether the red channel is clamped to ground or to midscale. the power-up default setting is 0. table 34. red clamp select bit value result 0 clamp to ground. 1 clamp to midscale. 0x18bit[2] green clamp select this bit determines whether the green channel is clamped to ground or to midscale. the power-up default setting is 0. table 35. green clamp select bit value result 0 clamp to ground. 1 clamp to midscale. 0x18bit[1] blue clamp select this bit determines whether the blue channel is clamped to ground or to midscale. the power-up default setting is 0. table 36. blue clamp select bit value result 0 clamp to ground. 1 clamp to midscale. 0x18bit[0] must be set to 0 for proper operation.
ad9984a rev. 0 | page 34 of 44 0x19bits[7:0] clamp placement an 8-bit register that sets the position of the internally generated clamp. when clamp source select = 0 (register 0x18, bit 4), a clamp signal is generated internally at a position established by this register and for a duration set by the clamp duration register (register 0x1a). clamping is started at the clamp placement count of pixel periods after the trailing edge of hsync. the clamp placement can be programmed to any value between 1 and 255. a value of 0 is not supported. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. when clamp source = 1, this register is ignored. power-up default setting is 8. 0x1abits[7:0] clamp duration an 8-bit register that sets the duration of the internally generated clamp. when the clamp source select is 0 (register 0x18, bit 4), a clamp signal is generated internally at a position established by the clamp placement register (register 0x19) for a duration set by this clamp duration register. clamping begins a clamp placement count (register 0x19) of pixel periods after the trailing edge of hsync. the clamp duration can be programmed to any value between 1 and 255. a value of 0 is not supported. for the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the hsync signal trailing edge. insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (apl) or brightness. when extclmp = 1, this register is ignored. power-up default setting is 20d. 0x1bbit[7] clamp polarity override this bit is used to override the internal circuitry that determines the polarity of the clamp signal. the power-up default setting is 0. table 37. clamp polarity override bit value result 0 clamp polarity determined by chip. 1 clamp polarity determined by user (register 0x1b, bit 6). 0x1bbit[6] clamp polarity this bit indicates the polarity of the clamp signal only if bit 7 of register 0x1b = 1. the power-up default setting is 1. table 38. clamp polarity bit value result 0 clamp polarity is negative. 1 clamp polarity is positive. 0x1bbit[5] auto-offset enable this bit selects between auto-offset mode and manual offset mode (auto-offset disabled). see the automatic offset section for more information. the power-up default setting is 0. table 39. auto-offset enable bit value result 0 auto-offset is disabled. 1 auto-offset is enabled (manual offset mode). 0x1bbits[4:3] auto-off set update frequency these bits control how often the auto-offset circuit is updated (if enabled). updating every 192 hsyncs recommended. the power-up default setting is 11. table 40. auto-offset update frequency bits value result 00 update offset every 3-clamp periods. 01 update offset every 48-clamp periods. 10 update offset every 192-clamp periods. 11 update offset every 3 vsync periods. 0x1bbits[2:0] must be written to 011 for proper operation. 0x1cbits[7:0] test register 0 must be set to 0xff for proper operation. sog control 0x1dbits[7:3] sog slicer comparator threshold these register bits adjust the comparator threshold of the sog slicer in steps of 8 mv, with the minimum setting equaling 8 mv and the maximum setting equaling 256 mv. the power- up default setting is 15d and corresponds to a threshold value of 128 mv. 0x1dbit[2] sogout polarity this bit sets the polarity of the sogout signal. the power-up default setting is 0. table 41. sogout polarity bit value result 0 sogout polarity is negative. 1 sogout polarity is positive. 0x1dbits[1:0] sogout select these register bits control what is output on the sogout pin. options are the raw soginx from the slicer (that is, the unproc- essed sog signal produced from the sync slicer), the raw hsyncx, the regenerated hsync from the sync filter that can generate missing syncs due to coasting or drop-out, or finally, the filtered hsync that excludes extraneous syncs that do not occur within the sync filter window. the power-up default setting is 0. table 42. sogout select bits value result 00 raw soginx. 01 raw hsyncx. 10 regenerated hsync from sync filter. 11 filtered hsync from sync filter.
ad9984a rev. 0 | page 35 of 44 input and power control 0x1ebit[7] channel select override this bit provides an override to the automatic input channel selection. power-up default setting is 0. table 43. channel select override bit value result 0 channel input source determined by chip. 1 channel input source determined by user, (register 0x1e, bit 6). 0x1ebit[6] channel select this bit selects the active input channel if bit 7 of register 0x1e is 1. this selects between channel 0 data and syncs or channel 1 data and syncs. power-up default setting is 0. table 44. channel select bit value result 0 channel 0 data and syncs are selected. 1 channel 1 data and syncs are selected. 0x1ebit[5] programmable bandwidth this bit selects between a low or high input bandwidth; having a low input bandwidth is useful in limiting noise for lower frequency inputs. the power-up default setting is 1. low analog input bandwidth is ~7 mhz; high analog input bandwidth is ~300 mhz. table 45. programmable bandwidth bit value result 0 low analog input bandwidth. 1 high analog input bandwidth. 0x1ebit[4] power-down control select this bit determines whether power-down is controlled manually or automatically by the chip. if automatic control is selected (by setting this bit to 1), the ad9984as decision is based on the status of the some of the sync detect bits (register 0x24, bit 2, bit 3, bit 6, and bit 7). if either an hsync or a sync-on-green input is detected on any input, the chip powers up or powers down. for manual control, the ad9984a allows the flexibility of control through both a dedicated pin and a register bit. the dedicated pin allows a hardware watchdog circuit to control power-down, whereas the register bit allows power-down to be controlled by software. with manual power-down control, the polarity of the power-down pin must be set (register 0x1e, bit 2) whether it is used or not. if unused, it is recommended to set the polarity to active high and hardwire the pin to ground with a 10 k resistor. table 46. power-down control select bit value result 0 manual power-down control (user determines power-down). 1 auto power-down control (chip determines power-down). 0x1ebit[3] power-down this bit is used to manually place the chip in power-down mode. it is only used if manual power-down control is selected (register 0x1e, bit 4 = 0). both the state of this register bit and the power-down pin (pin 17) are used to control manual power-down. (see the power management section for more details on power-down.) table 47. power-down bit value pin 17 result 0 0 normal operation. 1 x power-down. 0x1ebit[2] power-down pin polarity this bit defines the polarity of the power-down pin (pin 17). it is only used if manual power-down control is selected (register 0x1e, bit 4 = 0). table 48. power-down pin polarity bit value result 0 pwrdn polarity is negative. 1 pwrdn polarity is positive. 0x1ebit[1] power-down fast switching control this bit controls a special fast switching mode. with this bit, the ad9984a can stay active during power-down and only puts the outputs in high impedance. this option is useful when the data outputs from two chips are connected on a pcb and the user wants to instantaneously switch between the two. table 49. power-down fast switching control bit value result 0 normal power-down operation. 1 the chip stays powered up, and the outputs are put in high impedance mode. 0x1ebit[0] sogout hi gh impedance control this bit controls whether or not the sogout output pin is in high impedance when in power-down mode. in most cases, sogout is not put in high impedance during normal operation because it is usually needed for sync detection by the graphics controller. the option to put sogout in high impedance is included mainly to allow for factory testing modes. table 50. sogout high impedance control bit value result 0 the sogout operates as normal during power-down. 1 the sogout is in high impedance during power-down. output control 0x1fbits[7:5] output mode these bits choose between three options for the output mode. in 4:4:4 mode, rgb is standard. in 4:2:2 mode, ycbcr is standard, which reduces the number of output pins from 30 to 20. in 4:4:4 ddr output mode, the data is in rgb mode, but changes on every clock edge. the power-up default setting is 100.
ad9984a rev. 0 | page 36 of 44 table 51. output mode bits value result 100 4:4:4 rgb mode. 101 4:2:2 ycbcr mode. 110 4:4:4 ddr mode. 0x1fbit[4] primary output enable this bit places the primary output in active or high impedance mode. the power-up default setting is 1. table 52. primary output enable bit value result 0 primary output is in high impedance mode. 1 primary output is enabled. 0x1fbit[3] secondary output enable this bit places the secondary output in active or high impedance mode. the secondary output is designated when using either 4:2:2 or 4:4:4 ddr. in these modes, the data on the blue output channel is the secondary output while the output data on the red and green channels are the primary output. secondary output is always a ddr ycbcr data mode. see the output formatter section and table 12 . the power-up default setting is 0. table 53. secondary output enable bit value result 0 secondary output is in high impedance mode. 1 secondary output is enabled. 0x1fbits[2:1] output drive strength these two bits select the drive strength for all the high speed digital outputs (except vsout, a0, and o/e field). higher drive strength results in faster rise/fall times and, in general, makes it easier to capture data. lower drive strength results in slower rise/fall times and helps to reduce emi and digitally gen- erated power supply noise. the power-up default setting is 10. table 54. output drive strength bits value result 00 low output drive strength. 01 medium output drive strength. 1x high output drive strength. 0x1fbit[0] output clock invert this bit allows inversion of the output clock. the power-up default setting is 0. table 55. output clock invert bit value result 0 noninverted pixel clock. 1 inverted pixel clock. 0x20bits[7:6] output clock select these bits selects the optional output clocks such as a fixed 40 mhz internal clock, a 2 clock, a 90 phase-shifted clock, or the normal pixel clock. the power-up default setting is 00. table 56. output clock select bits value result 00 pixel clock. 01 90 phase-shifted pixel clock. 10 2 pixel clock. 11 0.5 pixel clock. 0x20bit[5] output high impedance this bit puts all outputs (except sogout) in a high impedance state. the power-up default setting is 0. table 57. output high impedance bit value result 0 normal outputs. 1 all outputs (except sogout) in high impedance mode. 0x20bit[4] sogout high impedance this bit allows the sogout pin to be placed in high impedance mode. the power-up default setting is 0. table 58. sogout high impedance bit value result 0 normal drive. 1 sogout pin is in high impedance mode. 0x20bit[3] field output polarity this bit sets the polarity of the field output bit. the power-up default setting is 1. table 59. field output polarity bit value result 0 active low = even field, active high = odd field. 1 active low = odd field, active high = even field. sync processing 0x20bit[2] pll sync filter enable this bit selects which signal the pll uses. it can select between raw versions of hsyncx/soginx and filtered versions of hsync/sog. the filtering of the hsync and sog can eliminate nearly all extraneous transitions that have traditionally caused pll disruption. the power-up default setting is 0. table 60. pll sync filter enable bit value result 0 pll uses raw hsyncx or soginx. 1 pll uses filtered hsync or sog. 0x20bit[1] sync processing input select this bit selects whether the sync processor uses a raw sync or a regenerated hsync for the following functions: coast, hsyncs per vsync count, field detection, and vsync duration counts. using the regenerated hsync is recommended. table 61. sync processing input select bit value result 0 sync processing uses raw hsyncx or soginx. 1 sync processing uses the internally regenerated hsync.
ad9984a rev. 0 | page 37 of 44 0x20bit[0] must be set to 1 for proper operation. 0x21bits[7:0] must be set to default. 0x22bits[7:0] must be set to default. 0x23bits[7:0] sync filter window width this 8-bit register sets the window of time for the regenerated hsync leading edge (in 25 ns steps) and the time that sync pulses are allowed to pass through. therefore, with the default value of 10, the window width is 250 ns. the goal is to set the window width to reject extraneous pulses (see the sync processing section). as with the sync separator threshold, the 25 ns multiplier value is somewhat variable. the maximum variability over all operating conditions is 20% (20 ns to 30 ns). detection status 0x24bit[7] hsync0 detection this bit is used to indicate when activity is detected on the hsync0 input pin. if hsync0 is held high or low, activity is not detected. the sync processing block diagram ( figure 9 ) shows where this function is implemented. table 62. hsync0 detection bit value result 0 no activity detected. 1 activity detected. 0x24bit[6] hsync1 detection this bit is used to indicate when activity is detected on the hsync1 input pin. if hsync1 is held high or low, activity is not detected. figure 9 shows where this function is implemented. table 63. hsync1 detection results value result 0 no activity detected. 1 activity detected. 0x24bit[5] vsync0 detection this bit is used to indicate when activity is detected on the vsync0 input pin. if vsync0 is held high or low, activity is not detected. figure 9 shows where this function is implemented. table 64. vsync0 detection results value result 0 no activity detected. 1 activity detected. 0x24bit[4] vsync1 detection this bit is used to indicate when activity is detected on the vsync1 input pin. if vsync1 is held high or low, activity is not detected. figure 9 shows where this function is implemented. table 65. vsync1 detection bit value result 0 no activity detected. 1 activity detected. 0x24bit[3] sogin0 detection this bit is used to indicate when activity is detected on the sogin0 pin. if sogin0 is held high or low, activity is not detected. figure 9 shows where this function is implemented. table 66. sogin0 detection bit value result 0 no activity detected. 1 activity detected. 0x24bit[2] sogin1 detection this bit is used to indicate when activity is detected on the sogin1 input pin. if sogin1 is held high or low, activity is not detected. figure 9 shows where this function is implemented. table 67. sogin1 detection bit value result 0 no activity detected. 1 activity detected. 0x24bit[1] coast detection this bit detects activity on the extck/coast pin. it indicates that one of the two signals is active, but it does not indicate which one. a dc signal is not detected. table 68. coast detection bit value result 0 no activity detected. 1 activity detected. 0x24bit[0] clamp detection this bit is used to indicate when activity is detected on the external clamp pin. if external clamp is held high or low, activity is not detected. table 69. clamp detection bit value result 0 no activity detected. 1 activity detected. polarity status 0x25bit[7] hsync0 polarity this bit indicates the polarity of hsync0 input. table 70. hsync0 polarity bit value result 0 hsync0 polarity is negative. 1 hsync0 polarity is positive.
ad9984a rev. 0 | page 38 of 44 0x25bit[6] hsync1 polarity this bit indicates the polarity of hsync1 input. table 71. hsync1 polarity bit value result 0 hsync1 polarity is negative. 1 hsync1 polarity is positive. 0x25bit[5] vsync0 polarity this bit indicates the polarity of vsync0 input. table 72. vsync0 polarity bit value result 0 vsync0 polarity is negative. 1 vsync0 polarity is positive. 0x25bit[4] vsync1 polarity this bit indicates the polarity of vsync1 input. table 73. vsync1 polarity bit value result 0 vsync1 polarity is negative. 1 vsync1 polarity is positive. 0x25bit[3] coast polarity this bit indicates the polarity of the external coast signal. table 74. coast polarity bit value result 0 coast polarity is negative. 1 coast polarity is positive. 0x25bit[2] clamp polarity this bit indicates the polarity of the clamp signal. table 75. clamp polarity bit value result 0 clamp polarity is negative. 1 clamp polarity is positive. 0x25bit[1] extraneous pulse detection a second output from the hsync filter, this status bit tells whether extraneous pulses are present on the incoming sync signal. often, extraneous pulses are used for copy protection, so this status bit can be used for this purpose. table 76. extraneous pulse detection bit value result 0 no extraneous pulses detected during active hsync. 1 extraneous pulses detected during active hsync. 0x25bit[0] sync filter lock when this bit is set to 1, the sync filter is locked. when set to 0, the sync filer is unlocked. hsync count 0x26bits[7:0] hsyncs per vsync msbs this register contains the 8 msbs of the 12-bit counter that reports the number of hsyncs per vsync on the active input. it is useful for determining the mode and is an aid in setting the pll divide ratio. 0x27bits[7:4] hsyncs per vsync lsbs this register contains the four lsbs of the 12-bit counter that reports the number of hsyncs per vsync on the active input. test registers 0x28bits[7:0] test register 1 must be written to 0xbf for proper operation. 0x29bits[7:0] test register 2 must be written to 0x02 for proper operation. 0x2abits[7:0] test register 3 read only bits for future use. 0x2bbits[7:0] test register 4 read only bits for future use. 0x2cbits[7:5] offset hold must be written to default 0x00 for proper operation. 0x2cbit[4] auto-offset hold this bit controls whether the auto-offset function runs continuously or only once and holds the result. continuous updates are recommended because they allow the ad9984a to compensate for drift over time, temperature, and so on. if one- time updates are preferred, they should be performed every time the part is powered up and when there is a mode change. to perform a one-time update, auto-offset must first be enabled (register 0x1b, bit 5). next, this bit (auto-offset hold) must first be set to 0 to let the auto-offset function operate and settle to a final value. auto-offset hold should then be set to 1 to hold the offset values that the auto circuitry calculates. the ad9984a auto-offset circuits maximum settle time is 10 updates. for example, if the update frequency is set to once every 192 hsyncs, the maximum settling time is 1920 hsyncs (10 192 hsyncs). table 77. auto-offset hold bit value result 0 allows auto-offset to continuously update. 1 disables auto-offset updates and holds the current auto-offset values. 0x2cbits[3:0] must be written to 0x0 for proper operation. 0x2dbits[7:0] test register 5 read/write bits for future use. must be written to 0xe8 for proper operation.
ad9984a rev. 0 | page 39 of 44 0x2ebits[7:0] test register 6 read/write bits for future use. must be written to 0xe0 for proper operation. 0x34bit[2] sog filter enabler when this bit is set to 1, the sog does not pass pulses less than 250 ns in width. this reduces spurious signals that can improperly drive the pll circuit. default for this bit is 0 or off. 0x36bit[0] vco gear select this bit allows the vco to select a lower gear to run lower pixel clocks while remaining in a more linear range. table 78. vco gear select bit value result 0 normal vco setting. 1 enables lower vco clock output. 0x3cbits[7:4] test bits must be set to 0x0 for proper operation. 0x3cbit[3] auto gain matching hold this bit controls whether the auto gain matching function runs continuously or runs once and holds the result. continuous updates are recommended because they allow the ad9984a to compensate for drift over time, temperature, and so on. if one-time updates are preferred, they should be performed every time the part is powered up and when there is a mode change. to perform a one-time update, auto gain matching must first be enabled (register 0x3c, bits[2:0]). next, this bit (auto gain matching hold) must first be set to 1 to let the auto gain matching function operate and settle to a final value. the auto gain matching hold bit should then be set to 0 to hold the gain values that the auto circuitry calculates. the ad9984a auto gain matching circuits maximum settle time is 10 updates. for example, if the update frequency is set to once every 64 hsyncs, the maximum settling time would be 640 hsyncs (10 64 hsyncs). table 79. auto gain matching hold bit value result 0 1 disables auto gain updates and holds the current auto gain values. 1 allows auto gain to update continuously. 1 the power-up default setting is 0. 0x3cbits[2:0] auto gain matching enable these bits enable or disable the auto gain matching function. table 80. auto gain matching enable bits value result 000 auto gain matching disabled. 110 auto gain matching enabled.
ad9984a rev. 0 | page 40 of 44 pcb layout recommendations the ad9984a is a high precision, high speed, analog device. to achieve the maximum performance from the part, it is important to have a well laid-out board. the section provides a guide for designing a board using the ad9984a. analog interface inputs use the following layout techniques on the graphics inputs: ? minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9984a as close as possible to the graphics vga connector. long input trace lengths are undesirable because they pick up noise from the board and other external sources. ? place the 75 termination resistors (see figure 4 ) as close as possible to the ad9984a chip. any additional trace length between the termination resistors and the input of the ad9984a increases the magnitude of reflections, which corrupts the graphics signal. ? use 75 matched impedance traces. trace impedances other than 75 also increase the chance of reflections. ? the ad9984a has a very high input bandwidth (300 mhz). while desirable for acquiring a high resolution pc graphics signal with fast edges, it also means that it captures any high frequency noise. therefore, it is important to reduce the amount of noise that is coupled to the inputs. avoid running any digital traces near the analog inputs. ? due to the high bandwidth of the ad9984a, using a low- pass filter with the analog inputs can help to reduce noise. (for many applications, filtering is unnecessary.) experiments have shown that placing a ferrite bead (specifically, the fair-rite 2508051217z0) in series prior to the 75 termination resistor is helpful in filtering excess noise. however, an application could work best with a different bead value. alternatively, placing a 100 to 120 resistor between the 75 termination resistor and the input coupling capacitor is beneficial. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. an exception is when two or more supply pins are adjacent to each other. for these groupings of powers/grounds, it is only necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within ~0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ad9984a, because doing so interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of the pv d (the clock generator supply). abrupt changes in pv d can result in similar changes in sampling clock phase and frequency. this can be avoided by paying careful attention to regulation, filtering, and bypassing. it is desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). some graphic controllers use substantially different levels of power when active (during active picture time), and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pv d , from a different, cleaner, power source (for example, from a 12 v supply). it is also recommended to use a single ground plane for the entire board. experience has repeatedly shown that noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. in some cases, using separate ground planes is unavoidable. for these cases, place at least a single ground plane under the part. the location of the split should be at the receiver of the digital outputs. in this case, it is even more important to place components wisely because the current loops become much longer (current takes the path of least resistance). an example of a current loop is power plane to ad9984a to digital output trace, to digital data receiver, to digital ground plane, to analog ground plane. pll place the pll loop filter components as close to the filt pin as possible. do not place any digital or other high frequency traces near these components. use the values suggested in the data sheet with 10% tolerances or less. outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance and require more instantaneous current to drive, which creates more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor of 50 to 200 can suppress reflections, reduce emi, and reduce the current spikes inside of the ad9984a. if series resistors are used, place them as close to the ad9984a pins as possible (although try not to add vias or extra length to the output trace to get the resistors closer). if possible, limit the capacitance driven by each digital output to less than 10 pf. this is easily accomplished by keeping traces short and connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside of the ad9984a and creates more digital noise on its power supplies.
ad9984a rev. 0 | page 41 of 44 digital inputs digital inputs on the ad9984a (hsync0, hsync1, vsync0, vsync1, sogin0, sogin1, sda, scl, and clamp) are designed to work with 3.3 v signals, but are tolerant of 5 v signals. therefore, no extra components need to be added if using 5 v logic. any noise that gets onto the hsync input trace adds jitter to the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. reference bypass the ad9984a has two reference voltages that must be bypassed for proper operation of the adc. reflo and refhi are connected to each other through a 10 f capacitor. these references are used by the adc circuitry to assure the greatest stability. place them as close to the ad9984a pin as possible.
ad9984a rev. 0 | page 42 of 44 outline dimensions compliant to jedec standards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 top view (pins down) pin 1 051706-a figure 20. 80-lead low profile quad flat package [lqfp] (st-80-2) dimensions shown in millimeters pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max * 4.85 4.70 sq 4.55 exposed pad (bottom view) * compliant to jedec standards mo-220-vmmd-4 except for exposed pad dimension 063006-b seating plane pin 1 indicator 0.30 0.25 0.18 figure 21. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm x 9 mm body, very thin quad (cp-64-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9984akstz-140 1 0c to 70c 80-lead low profile quad flat package [lqfp] st-80-2 ad9984akstz-170 1 0c to 70c 80-lead low profile quad flat package [lqfp] st-80-2 ad9984akcpz-140 1 0c to 70c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-1 ad9984akcpz-170 1 0c to 70c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-1 ad9984a/pcbz 1 evaluation board [lqfp] 1 z = rohs compliant part.
ad9984a rev. 0 | page 43 of 44 notes
ad9984a rev. 0 | page 44 of 44 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06476-0- 7/07(0)

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